62 lines
1.8 KiB
Verilog
62 lines
1.8 KiB
Verilog
/////////////////////////////////////////////////////////////////////////////
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// _____
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// / _______ Copyright (C) 2013-2020 Efinix Inc. All rights reserved.
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// / / \
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// / / .. /
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// / / .' /
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// __/ /.' /
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// __ \ /
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// /_/ /\ \_____/ /
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// ____/ \_______/
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//
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// *******************************
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// Revisions:
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// 1.0 Initial rev
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//
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// *******************************
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`timescale 1 ns / 1 ns
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module axi4_st_mux
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(
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//Globle Signals
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input mux_select,
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//Mux In 0 Interface
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input [7:0] tdata0,
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input tvalid0,
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input tlast0,
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input tuser0,
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output wire tready0,
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//Mux In 1 Interface
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input [7:0] tdata1,
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input tvalid1,
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input tlast1,
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input tuser1,
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output wire tready1,
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//Mux Out Interface
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output wire [7:0] tdata,
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output wire tvalid,
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output wire tlast,
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output wire tuser,
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input tready
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);
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// Parameter Define
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// Register Define
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// Wire Define
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/*----------------------------------------------------------------------------------*\
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The main code
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\*----------------------------------------------------------------------------------*/
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assign tdata = (mux_select) ? tdata1 : tdata0;
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assign tvalid = (mux_select) ? tvalid1 : tvalid0;
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assign tlast = (mux_select) ? tlast1 : tlast0;
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assign tuser = (mux_select) ? tuser1 : tuser0;
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assign tready0 = (mux_select) ? 1'b1 : tready;
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assign tready1 = (mux_select) ? tready : 1'b1;
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endmodule
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