AXIL Shadow Register

A shadow register interface that lets you write atomically with a larger width, i.e. 8 bit to 32 bits.

mentioned in issue super6502#91 (closed)

So written description I guess.

When we are writing to any bytes other than the LSB, shadow register will accept the data. When we are writing the the LSB, then the AXI signals are passed through except wstrb is set to all 1s and the wdata is replaced with the shadow data for the upper bytes

Here is the basic idea.

created branch 4-axil-shadow-register to address this issue

mentioned in merge request !3

Ok I had to refactor a ton if this to actually work in my situation with super6502, but I don't really care lol. It works based off of the write strobe, not the lsbs of the address. Those are invalid anyway if they are not 0.