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SDRAM Controller
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Byron Lathi
SDRAM Controller
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Created with Raphaël 2.2.0
20
Jan
19
18
Rename _200 to _sys
master
master
Add FPGA
Add top level
Finish write/read sdram_phy tests
Fix gitmodules
Add sdram phy and start tests
Add FIFO
Add single read and single write
Refactor, start of read/write
Add autorefresh logic
Add init sequence
Add read part
split read and write queues
Rename axi interface file, add write sims
Add sim
Add detail to refresh generator
Update docs, add start of code
Add diagram
Initial Commit, Add Design Document
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