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commented on issue #4 "Pass timing on Trion" at Byron Lathi / SDRAM Controller

So the phy can operate in basically the same way, and we can insert NOPs after the commands, but the one case where we cannot do this is when we ar...

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pushed to branch master at Byron Lathi / SDRAM Controller
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pushed to branch master at Byron Lathi / SDRAM Controller
Byron Lathi's avatar
commented on issue #4 "Pass timing on Trion" at Byron Lathi / SDRAM Controller

Ideally, we would be able to support running at 200MHz on titanium FPGAs though. Depending on how much logic needs to be redone in the PHY, it migh...

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opened issue #4 "Pass timing on Trion" at Byron Lathi / SDRAM Controller
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opened issue #3 "test top level" at Byron Lathi / SDRAM Controller
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pushed to branch master at Byron Lathi / SDRAM Controller
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pushed to branch master at Byron Lathi / SDRAM Controller
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pushed to branch master at Byron Lathi / SDRAM Controller
  • f06ea404 · Finish write/read sdram_phy tests
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opened issue #2 "Write (and probably read) are hard coded for burst length 2" at Byron Lathi / SDRAM Controller
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pushed to branch master at Byron Lathi / SDRAM Controller
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pushed to branch master at Byron Lathi / SDRAM Controller
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pushed to branch master at Byron Lathi / SDRAM Controller
  • 9674d948 · Add single read and single write
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pushed to branch master at Byron Lathi / SDRAM Controller
  • 81b39340 · Refactor, start of read/write
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pushed to branch master at Byron Lathi / SDRAM Controller
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pushed to branch master at Byron Lathi / SDRAM Controller
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pushed to branch master at Byron Lathi / SDRAM Controller
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closed issue #1 "Split read/write queues" at Byron Lathi / SDRAM Controller
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commented on issue #1 "Split read/write queues" at Byron Lathi / SDRAM Controller

addressed in a0db586e

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pushed to branch master at Byron Lathi / SDRAM Controller
  • a0db586e · split read and write queues