Commits · master · Byron Lathi / SDRAM Controller

Jan 21, 2025
- Rename _200 to _sys · 1ce3a940
  Byron Lathi authored 2 months ago
  
  In preparation for double clock phy
  1ce3a940
Jan 20, 2025
- Add FPGA · d3de9378
  Byron Lathi authored 2 months ago
  
  d3de9378
- Add top level · d93d550b
  Byron Lathi authored 2 months ago
  
  d93d550b
- Finish write/read sdram_phy tests · f06ea404
  Byron Lathi authored 2 months ago
  
  f06ea404
- Fix gitmodules · 092e6c49
  Byron Lathi authored 2 months ago
  
  092e6c49
- Add sdram phy and start tests · 5754dbca
  Byron Lathi authored 2 months ago
  
  5754dbca
- Add FIFO · 5b40c2c2
  Byron Lathi authored 2 months ago
  
  for sim and example project only
  5b40c2c2
- Add single read and single write · 9674d948
  Byron Lathi authored 2 months ago
  
  9674d948
- Refactor, start of read/write · 81b39340
  Byron Lathi authored 2 months ago
  
  81b39340
- Add autorefresh logic · 1963861c
  Byron Lathi authored 2 months ago
  
  1963861c
- Add init sequence · 00354bc6
  Byron Lathi authored 2 months ago
  
  00354bc6
Jan 19, 2025
- Add read part · e728c827
  Byron Lathi authored 2 months ago
  
  e728c827
- split read and write queues · a0db586e
  Byron Lathi authored 2 months ago
  
  a0db586e
- Rename axi interface file, add write sims · 916db14c
  Byron Lathi authored 2 months ago
  
  916db14c
- Add sim · 9f357fe7
  Byron Lathi authored 2 months ago
  
  9f357fe7
- Add detail to refresh generator · fe763dc0
  Byron Lathi authored 2 months ago
  
  Verified
  
  fe763dc0
- Update docs, add start of code · 92f0218a
  Byron Lathi authored 2 months ago
  
  Verified
  
  92f0218a
- Add diagram · 8cf31ec0
  Byron Lathi authored 2 months ago
  
  Verified
  
  8cf31ec0
- Initial Commit, Add Design Document · 191aec57
  Byron Lathi authored 2 months ago
  
  Verified
  
  191aec57