Add submodule back

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Byron Lathi

2023-09-23 09:59:39 -07:00

parent 77dd4f1002

commit 00173f4e89

2 changed files with 5 additions and 1 deletions

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hw/efinix_fpga/simulation/src/verilog-6502 Submodule

Submodule hw/efinix_fpga/simulation/src/verilog-6502 added at a5f605d00d