Get block rom working
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@@ -3,12 +3,12 @@
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{
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"name": "la0",
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"type": "la",
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"uuid": "2ec8ec3d274747939b82c28997a2ef1d",
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"uuid": "244dbd2d34ea40fba571b257d0a2bb75",
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"trigin_en": false,
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"trigout_en": false,
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"auto_inserted": true,
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"capture_control": false,
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"data_depth": 128,
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"data_depth": 1024,
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"input_pipeline": 1,
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"probes": [
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{
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@@ -422,7 +422,7 @@
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],
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"session": {
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"wizard": {
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"data_depth": 128,
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"data_depth": 1024,
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"capture_control": false,
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"selected_nets": [
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{
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@@ -16,7 +16,7 @@ module super6502
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output logic cpu_rdy,
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output logic cpu_resb,
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output logic pll_cpu_reset,
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output logic cpu_phi2
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output logic cpu_phi2,
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);
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assign pll_cpu_reset = '1;
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@@ -26,9 +26,7 @@ assign cpu_rdy = '1;
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assign cpu_irqb = '1;
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assign cpu_nmib = '1;
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always @(posedge clk_2) begin
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cpu_phi2 <= ~cpu_phi2;
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end
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assign cpu_phi2 = clk_2;
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always @(posedge clk_2) begin
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if (button_reset == '0) begin
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@@ -1,5 +1,5 @@
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<?xml version="1.0" encoding="UTF-8"?>
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<efx:project name="super6502" description="" last_change_date="Tue December 20 2022 15:37:23" location="/home/byron/Projects/super6502/hw/efinix_fpga" sw_version="2022.1.226" last_run_state="pass" last_run_tool="efx_pgm" last_run_flow="bitstream" config_result_in_sync="true" design_ood="sync" place_ood="sync" route_ood="sync" xmlns:efx="http://www.efinixinc.com/enf_proj" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:schemaLocation="http://www.efinixinc.com/enf_proj enf_proj.xsd">
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<efx:project name="super6502" description="" last_change_date="Tue December 20 2022 17:26:24" location="/home/byron/Projects/super6502/hw/efinix_fpga" sw_version="2022.1.226" last_run_state="pass" last_run_tool="efx_pgm" last_run_flow="bitstream" config_result_in_sync="true" design_ood="change" place_ood="sync" route_ood="sync" xmlns:efx="http://www.efinixinc.com/enf_proj" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:schemaLocation="http://www.efinixinc.com/enf_proj enf_proj.xsd">
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<efx:device_info>
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<efx:family name="Trion"/>
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<efx:device name="T20F256"/>
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