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Get block rom working

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This commit is contained in:
Byron Lathi
2022-12-20 17:26:59 -05:00
parent 52de8d3eb3
commit 12fb6283cc
3 changed files with 6 additions and 8 deletions
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6
hw/efinix_fpga/debug_profile.wizard.json
View File

@@ -3,12 +3,12 @@
{ {
"name": "la0", "name": "la0",
"type": "la", "type": "la",
"uuid": "2ec8ec3d274747939b82c28997a2ef1d", "uuid": "244dbd2d34ea40fba571b257d0a2bb75",
"trigin_en": false, "trigin_en": false,
"trigout_en": false, "trigout_en": false,
"auto_inserted": true, "auto_inserted": true,
"capture_control": false, "capture_control": false,
"data_depth": 128, "data_depth": 1024,
"input_pipeline": 1, "input_pipeline": 1,
"probes": [ "probes": [
{ {
@@ -422,7 +422,7 @@
], ],
"session": { "session": {
"wizard": { "wizard": {
"data_depth": 128, "data_depth": 1024,
"capture_control": false, "capture_control": false,
"selected_nets": [ "selected_nets": [
{ {

6
hw/efinix_fpga/super6502.sv
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@@ -16,7 +16,7 @@ module super6502
output logic cpu_rdy, output logic cpu_rdy,
output logic cpu_resb, output logic cpu_resb,
output logic pll_cpu_reset, output logic pll_cpu_reset,
output logic cpu_phi2 output logic cpu_phi2,
); );
assign pll_cpu_reset = '1; assign pll_cpu_reset = '1;
@@ -26,9 +26,7 @@ assign cpu_rdy = '1;
assign cpu_irqb = '1; assign cpu_irqb = '1;
assign cpu_nmib = '1; assign cpu_nmib = '1;
always @(posedge clk_2) begin assign cpu_phi2 = clk_2;
cpu_phi2 <= ~cpu_phi2;
end
always @(posedge clk_2) begin always @(posedge clk_2) begin
if (button_reset == '0) begin if (button_reset == '0) begin

2
hw/efinix_fpga/super6502.xml
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@@ -1,5 +1,5 @@
<?xml version="1.0" encoding="UTF-8"?> <?xml version="1.0" encoding="UTF-8"?>
<efx:project name="super6502" description="" last_change_date="Tue December 20 2022 15:37:23" location="/home/byron/Projects/super6502/hw/efinix_fpga" sw_version="2022.1.226" last_run_state="pass" last_run_tool="efx_pgm" last_run_flow="bitstream" config_result_in_sync="true" design_ood="sync" place_ood="sync" route_ood="sync" xmlns:efx="http://www.efinixinc.com/enf_proj" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:schemaLocation="http://www.efinixinc.com/enf_proj enf_proj.xsd"> <efx:project name="super6502" description="" last_change_date="Tue December 20 2022 17:26:24" location="/home/byron/Projects/super6502/hw/efinix_fpga" sw_version="2022.1.226" last_run_state="pass" last_run_tool="efx_pgm" last_run_flow="bitstream" config_result_in_sync="true" design_ood="change" place_ood="sync" route_ood="sync" xmlns:efx="http://www.efinixinc.com/enf_proj" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:schemaLocation="http://www.efinixinc.com/enf_proj enf_proj.xsd">
<efx:device_info> <efx:device_info>
<efx:family name="Trion"/> <efx:family name="Trion"/>
<efx:device name="T20F256"/> <efx:device name="T20F256"/>