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Merge branch '31-show-uart-messages-in-sim-log' into 'master'

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Resolve "Show UART messages in sim log"

Closes #31

See merge request bslathi19/super6502!24
This commit is contained in:
Byron Lathi
2023-09-28 06:14:00 +00:00
parent a76763bdc7 85f53816f9
commit 1b838169d3
11 changed files with 193 additions and 146 deletions
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52
hw/efinix_fpga/init_hex.mem
View File

@@ -38,32 +38,32 @@ F2 68 60 A9 01 8D DB EF 60 9C DB EF 60 A9 00 8D
DA EF AD DB EF 30 FB AD D9 EF 60 8D E6 EF 60 48
8D E6 EF AD E7 EF 89 02 D0 F9 68 60 AD E6 EF A2
00 60 AD E7 EF A2 00 60 60 20 74 FB A2 00 86 06
86 07 A9 00 20 0B FC 20 5A FB A9 89 A2 FE 20 1A
FB 20 3A F3 C9 00 20 B8 FC D0 03 4C 98 F2 A9 81
A2 FE 20 1A FB 4C 2E F3 A9 77 A2 FE 20 1A FB A0
86 07 A9 00 20 0B FC 20 5A FB A9 86 A2 FE 20 1A
FB 20 3A F3 C9 00 20 B8 FC D0 03 4C 98 F2 A9 7F
A2 FE 20 1A FB 4C 2E F3 A9 76 A2 FE 20 1A FB A0
05 20 C7 FB 20 0B FC AD 00 92 AE 01 92 20 4D FD
A9 0C 20 D8 FB 20 96 F1 A0 07 91 04 A0 07 A2 00
B1 04 C9 00 20 BE FC D0 03 4C DC F2 A0 06 A2 00
B1 04 C9 FE 20 BE FC F0 03 4C E5 F2 A2 00 A9 00
D0 03 4C E9 F2 A2 00 A9 01 D0 03 4C FA F2 AD 00
92 AE 01 92 20 3C F6 4C 2B F3 A0 06 A2 00 B1 04
A2 00 29 F0 20 9F FA D0 03 4C 16 F3 A9 81 A2 FE
A2 00 29 F0 20 9F FA D0 03 4C 16 F3 A9 7F A2 FE
20 1A FB 4C 2B F3 A9 67 A2 FE 20 4D FD A0 08 A2
00 B1 04 20 4D FD A0 04 20 E6 FA 6C 00 92 4C 31
F3 4C 31 F3 A0 0C 20 85 FA 60 20 81 FB A9 00 20
37 FD 20 6E F1 4C 71 F3 A0 00 A2 00 18 A9 01 71
04 91 04 A0 00 A2 00 B1 04 C9 FF 20 BE FC D0 03
4C 71 F3 A9 AB A2 FE 20 1A FB A2 00 A9 01 4C A8
4C 71 F3 A9 A5 A2 FE 20 1A FB A2 00 A9 01 4C A8
F4 20 AC F4 A0 01 91 04 C9 01 20 B8 FC D0 C9 A2
00 A9 00 A0 06 20 65 FD A0 07 20 BE FB E0 03 D0
02 C9 E8 20 D7 FC F0 03 4C 9E F3 4C AA F3 A0 06
A2 00 A9 01 20 75 FA 4C 88 F3 A9 01 20 D8 FB 20
C9 F4 A0 01 A2 00 B1 04 C9 01 20 B8 FC D0 03 4C
D0 F3 A9 A1 A2 FE 20 1A FB A2 00 A9 01 4C A8 F4
D0 F3 A9 9C A2 FE 20 1A FB A2 00 A9 01 4C A8 F4
A0 05 A2 00 B1 04 C9 AA 20 B8 FC D0 03 4C E7 F3
A2 00 A9 01 4C A8 F4 A2 00 A9 00 A0 00 91 04 A0
00 A2 00 B1 04 C9 FF 20 BE FC D0 03 4C 0D F4 A9
91 A2 FE 20 1A FB A2 00 A9 01 4C A8 F4 20 EB F5
8D A2 FE 20 1A FB A2 00 A9 01 4C A8 F4 20 EB F5
A0 01 91 04 A0 01 A2 00 B1 04 C9 02 20 D7 FC D0
03 4C 2B F4 20 08 F6 A0 01 91 04 A2 00 A9 00 A0
06 20 65 FD A0 07 20 BE FB E0 03 D0 02 C9 E8 20
@@ -101,13 +101,13 @@ A2 00 A9 FF 20 3F F2 20 A4 FB 60 A2 00 A9 37 20
00 B1 04 4C 36 F6 A0 0E 20 85 FA 60 20 4D FD A9
00 20 37 FD 20 5A FB A2 00 A9 00 A0 00 20 65 FD
A0 01 20 BE FB E0 02 20 D7 FC F0 03 4C 62 F6 4C
C4 F6 A9 B5 A2 FE 20 4D FD A0 06 20 BE FB A0 00
C4 F6 A9 AE A2 FE 20 4D FD A0 06 20 BE FB A0 00
20 B3 FB 20 4D FD A0 07 A2 00 A9 01 20 75 FA A0
04 20 E6 FA A0 02 A2 00 B1 04 C9 1F 20 BE FC D0
03 4C A6 F6 A9 B9 A2 FE 20 1A FB A2 00 A9 00 A0
03 4C A6 F6 A9 B2 A2 FE 20 1A FB A2 00 A9 00 A0
02 91 04 4C B8 F6 A2 00 A9 20 20 68 F0 A0 02 A2
00 18 A9 01 71 04 91 04 A0 00 A2 00 A9 01 20 75
FA 4C 50 F6 A9 B9 A2 FE 20 1A FB 20 A9 FB 60 A0
FA 4C 50 F6 A9 B2 A2 FE 20 1A FB 20 A9 FB 60 A0
00 B1 1A E6 1A D0 02 E6 1B 60 AD 4A 92 8D 45 92
20 7B F7 A9 45 A2 92 20 4D FD 20 2E FD 4C 02 92
A5 18 38 E9 02 85 18 B0 02 C6 19 60 AD 4F 92 D0
@@ -178,8 +178,8 @@ F0 E6 14 D0 EF 60 8C 6A 92 88 88 98 18 65 04 85
20 4D FD A5 0C A6 0D 20 14 FE AC 6A 92 4C 85 FA
85 0C 86 0D 20 75 F0 4C 1E FB 85 0C 86 0D A0 00
B1 0C F0 0E C8 84 14 20 68 F0 A4 14 D0 F2 E6 0D
D0 EE 60 E0 00 D0 15 4A AA BD E3 FE 90 05 4A 4A
4A 4A 18 29 0F AA BD D8 FE A2 00 60 38 A9 00 AA
D0 EE 60 E0 00 D0 15 4A AA BD DB FE 90 05 4A 4A
4A 4A 18 29 0F AA BD D0 FE A2 00 60 38 A9 00 AA
60 A4 04 D0 02 C6 05 C6 04 60 A5 04 38 E9 02 85
04 90 01 60 C6 05 60 A5 04 38 E9 04 85 04 90 01
60 C6 05 60 A5 04 38 E9 06 85 04 90 01 60 C6 05
@@ -196,11 +196,11 @@ A5 06 49 FF 69 00 85 06 A5 07 49 FF 69 00 85 07
91 04 60 85 14 20 8E FB 85 0E 86 0F 85 10 86 11
20 20 FD 20 8E FB 85 06 86 07 60 20 23 FC A6 07
A4 14 C0 0A D0 39 A5 06 05 0D 05 0C D0 11 E0 80
D0 0D A0 0B B9 CC FE 91 0E 88 10 F8 4C B3 FC 8A
D0 0D A0 0B B9 C4 FE 91 0E 88 10 F8 4C B3 FC 8A
10 1D A9 2D A0 00 91 0E E6 0E D0 02 E6 0F A5 0C
A6 0D 20 E4 FB 85 0C 86 0D 4C 7F FC 20 23 FC A9
00 48 A0 20 A9 00 06 0C 26 0D 26 06 26 07 2A C5
14 90 04 E5 14 E6 0C 88 D0 EC A8 B9 BC FE 48 A5
14 90 04 E5 14 E6 0C 88 D0 EC A8 B9 B4 FE 48 A5
0C 05 0D 05 06 05 07 D0 D9 A0 00 68 91 0E F0 03
C8 D0 F8 A5 10 A6 11 60 D0 06 A2 00 8A 60 D0 FA
A2 00 A9 01 60 F0 F9 30 F7 A2 00 8A 60 F0 02 10
@@ -230,18 +230,18 @@ A0 01 B1 04 AA 88 B1 04 20 4D FD A0 02 A9 2A 91
AE 2B 92 60 A9 32 85 0C A9 92 85 0D A9 00 A8 A2
00 F0 0A 91 0C C8 D0 FB E6 0D CA D0 F6 C0 39 F0
05 91 0C C8 D0 F7 60 62 61 64 20 74 6F 6B 65 6E
3A 20 25 78 0D 0A 00 53 75 63 63 65 73 73 0D 0A
00 45 72 72 6F 72 0D 0A 00 53 74 61 72 74 0D 0A
00 6F 70 5F 63 6F 6E 64 20 65 72 72 6F 72 0D 0A
00 49 46 20 43 6F 6E 64 0D 0A 00 47 6F 20 49 44
4C 45 0D 0A 00 25 32 78 00 0D 0A 00 30 31 32 33
34 35 36 37 38 39 41 42 43 44 45 46 2D 32 31 34
37 34 38 33 36 34 38 00 00 01 02 0C 09 0A 10 40
50 A0 D0 66 66 66 66 A6 88 88 66 66 66 66 66 66
66 66 66 09 00 00 00 00 00 00 00 33 33 33 33 33
00 00 00 50 55 55 25 22 22 22 22 22 22 22 22 22
02 00 00 40 44 44 14 11 11 11 11 11 11 11 11 11
01 00 70 00 00 00 00 00 00 00 00 00 00 00 00 00
3A 20 25 78 0A 00 53 75 63 63 65 73 73 0A 00 45
72 72 6F 72 0A 00 53 74 61 72 74 0A 00 6F 70 5F
63 6F 6E 64 20 65 72 72 6F 72 0A 00 49 46 20 43
6F 6E 64 0A 00 47 6F 20 49 44 4C 45 0A 00 25 32
78 00 0A 00 30 31 32 33 34 35 36 37 38 39 41 42
43 44 45 46 2D 32 31 34 37 34 38 33 36 34 38 00
00 01 02 0C 09 0A 10 40 50 A0 D0 66 66 66 66 A6
88 88 66 66 66 66 66 66 66 66 66 09 00 00 00 00
00 00 00 33 33 33 33 33 00 00 00 50 55 55 25 22
22 22 22 22 22 22 22 22 02 00 00 40 44 44 14 11
11 11 11 11 11 11 11 11 01 00 70 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00

163
hw/efinix_fpga/simulation/src/sim_top.sv
View File

@@ -8,34 +8,34 @@ logic r_sysclk, r_sdrclk, r_clk_50, r_clk_2;
// clk_100
initial begin
r_sysclk <= '1;
forever begin
#5 r_sysclk <= ~r_sysclk;
end
r_sysclk <= '1;
forever begin
#5 r_sysclk <= ~r_sysclk;
end
end
// clk_200
initial begin
r_sdrclk <= '1;
forever begin
#2.5 r_sdrclk <= ~r_sdrclk;
end
r_sdrclk <= '1;
forever begin
#2.5 r_sdrclk <= ~r_sdrclk;
end
end
// clk_50
initial begin
r_clk_50 <= '1;
forever begin
#10 r_clk_50 <= ~r_clk_50;
end
r_clk_50 <= '1;
forever begin
#10 r_clk_50 <= ~r_clk_50;
end
end
// clk_2
initial begin
r_clk_2 <= '1;
forever begin
#250 r_clk_2 <= ~r_clk_2;
end
r_clk_2 <= '1;
forever begin
#250 r_clk_2 <= ~r_clk_2;
end
end
initial begin
@@ -46,11 +46,11 @@ end
logic button_reset;
initial begin
button_reset <= '0;
repeat(10) @(r_clk_2);
button_reset <= '1;
repeat(20000) @(r_clk_2);
$finish();
button_reset <= '0;
repeat(10) @(r_clk_2);
button_reset <= '1;
repeat(20000) @(r_clk_2);
$finish();
end
logic w_cpu_reset;
@@ -62,53 +62,55 @@ logic w_cpu_phi2;
//TODO: this
cpu_65c02 u_cpu(
.phi2(w_cpu_phi2),
.reset(~w_cpu_reset),
.AB(w_cpu_addr),
.RDY(w_cpu_rdy),
.IRQ('0),
.NMI('0),
.DI_s1(w_cpu_data_from_dut),
.DO(w_cpu_data_from_cpu),
.WE(w_cpu_we)
.phi2(w_cpu_phi2),
.reset(~w_cpu_reset),
.AB(w_cpu_addr),
.RDY(w_cpu_rdy),
.IRQ('0),
.NMI('0),
.DI_s1(w_cpu_data_from_dut),
.DO(w_cpu_data_from_cpu),
.WE(w_cpu_we)
);
logic w_dut_uart_rx, w_dut_uart_tx;
sim_uart u_sim_uart(
.clk_50(r_clk_50),
.reset(~w_cpu_reset),
.rx_i(w_dut_uart_tx),
.tx_o(w_dut_uart_rx)
);
// Having the super6502 causes an infinite loop,
// but just the rom works. Need to whittle down
// which block is causing it.
// rom #(.DATA_WIDTH(8), .ADDR_WIDTH(12)) u_rom(
// .addr(w_cpu_addr[11:0]),
// .clk(r_clk_2),
// .data(w_cpu_data_from_dut)
// );
//TODO: also this
super6502 u_dut(
.i_sysclk(r_sysclk),
.i_sdrclk(r_sdrclk),
.i_tACclk(~r_sdrclk),
.clk_50(r_clk_50),
.clk_2(r_clk_2),
.button_reset(button_reset),
.cpu_resb(w_cpu_reset),
.cpu_addr(w_cpu_addr),
.cpu_data_out(w_cpu_data_from_dut),
.cpu_data_in(w_cpu_data_from_cpu),
.cpu_rwb(~w_cpu_we),
.cpu_rdy(w_cpu_rdy),
.cpu_phi2(w_cpu_phi2),
.i_sysclk(r_sysclk),
.i_sdrclk(r_sdrclk),
.i_tACclk(~r_sdrclk),
.clk_50(r_clk_50),
.clk_2(r_clk_2),
.button_reset(button_reset),
.cpu_resb(w_cpu_reset),
.cpu_addr(w_cpu_addr),
.cpu_data_out(w_cpu_data_from_dut),
.cpu_data_in(w_cpu_data_from_cpu),
.cpu_rwb(~w_cpu_we),
.cpu_rdy(w_cpu_rdy),
.cpu_phi2(w_cpu_phi2),
.o_sdr_CKE(w_sdr_CKE),
.o_sdr_n_CS(w_sdr_n_CS),
.o_sdr_n_WE(w_sdr_n_WE),
.o_sdr_n_RAS(w_sdr_n_RAS),
.o_sdr_n_CAS(w_sdr_n_CAS),
.o_sdr_BA(w_sdr_BA),
.o_sdr_ADDR(w_sdr_ADDR),
.i_sdr_DATA(w_sdr_DQ),
.o_sdr_DATA(w_sdr_DATA),
.o_sdr_DATA_oe(w_sdr_DATA_oe),
.uart_rx(w_dut_uart_rx),
.uart_tx(w_dut_uart_tx),
.o_sdr_CKE(w_sdr_CKE),
.o_sdr_n_CS(w_sdr_n_CS),
.o_sdr_n_WE(w_sdr_n_WE),
.o_sdr_n_RAS(w_sdr_n_RAS),
.o_sdr_n_CAS(w_sdr_n_CAS),
.o_sdr_BA(w_sdr_BA),
.o_sdr_ADDR(w_sdr_ADDR),
.i_sdr_DATA(w_sdr_DQ),
.o_sdr_DATA(w_sdr_DATA),
.o_sdr_DATA_oe(w_sdr_DATA_oe),
.o_sdr_DQM(w_sdr_DQM)
);
@@ -126,29 +128,28 @@ wire [DQ_GROUP *DQ_WIDTH -1:0]w_sdr_DQ;
genvar i, j;
generate
for (i=0; i<DQ_GROUP*DQ_WIDTH; i=i+1)
begin: DQ_map
assign w_sdr_DQ[i] = (w_sdr_DATA_oe[i])?
w_sdr_DATA[i]:1'bz;
end
for (i=0; i<DQ_GROUP*DQ_WIDTH; i=i+1)
begin: DQ_map
assign w_sdr_DQ[i] = (w_sdr_DATA_oe[i])?
w_sdr_DATA[i]:1'bz;
end
for (j=0; j<DQ_GROUP; j=j+1)
begin : mem_inst
for (j=0; j<DQ_GROUP; j=j+1)
begin : mem_inst
generic_sdr inst_sdr
(
.Dq(w_sdr_DQ[((j+1)*(DQ_WIDTH))-1:((j)*DQ_WIDTH)]),
.Addr(w_sdr_ADDR[ROW_WIDTH-1:0]),
.Ba(w_sdr_BA[BA_WIDTH-1:0]),
.Clk(~r_sdrclk),
.Cke(w_sdr_CKE),
.Cs_n(w_sdr_n_CS),
.Ras_n(w_sdr_n_RAS),
.Cas_n(w_sdr_n_CAS),
.We_n(w_sdr_n_WE),
.Dqm(w_sdr_DQM[j])
.Dq(w_sdr_DQ[((j+1)*(DQ_WIDTH))-1:((j)*DQ_WIDTH)]),
.Addr(w_sdr_ADDR[ROW_WIDTH-1:0]),
.Ba(w_sdr_BA[BA_WIDTH-1:0]),
.Clk(~r_sdrclk),
.Cke(w_sdr_CKE),
.Cs_n(w_sdr_n_CS),
.Ras_n(w_sdr_n_RAS),
.Cas_n(w_sdr_n_CAS),
.We_n(w_sdr_n_WE),
.Dqm(w_sdr_DQM[j])
);
end
endgenerate
endmodule

43
hw/efinix_fpga/simulation/src/sim_uart/sim_uart.sv Normal file
View File

@@ -0,0 +1,43 @@
module sim_uart(
input clk,
input clk_50,
input reset,
input [7:0] i_data,
input rx_i,
output tx_o
);
logic tx_busy, rx_busy;
logic rx_data_valid, rx_error, rx_parity_error;
logic baud_x16_ce;
logic tx_en;
logic [7:0] tx_data, rx_data;
uart u_uart(
.tx_o ( tx_o ),
.rx_i ( rx_i ),
.tx_busy ( tx_busy ),
.rx_data ( rx_data ),
.rx_data_valid ( rx_data_valid ),
.rx_error ( rx_error ),
.rx_parity_error ( rx_parity_error ),
.rx_busy ( rx_busy ),
.baud_x16_ce ( baud_x16_ce ),
.clk ( clk_50 ),
.reset ( reset ),
.tx_data ( tx_data ),
.baud_rate ( baud_rate ),
.tx_en ( tx_en )
);
always @(posedge baud_x16_ce) begin
if (rx_data_valid)
$display("UART: %c", rx_data);
end
endmodule

35
hw/efinix_fpga/src/uart_wrapper.sv
View File

@@ -48,30 +48,33 @@ always_ff @(posedge clk_50) begin
if (reset) begin
state <= READY;
irqb <= '1;
status <= '0;
end else begin
state <= next_state;
end
end
always_ff @(negedge clk) begin
status[1] <= tx_busy | tx_en;
if (reset) begin
status <= '0;
end else begin
status[1] <= tx_busy | tx_en;
status[0] <= status[0] | rx_data_valid;
if (cs & ~addr & rwb) begin
status[0] <= 0;
end
status[0] <= status[0] | rx_data_valid;
if (cs & ~addr & rwb) begin
status[0] <= 0;
end
if (cs & ~rwb) begin
case (addr)
1'b0: begin
tx_data <= i_data;
end
if (cs & ~rwb) begin
case (addr)
1'b0: begin
tx_data <= i_data;
end
1'b1: begin
control <= i_data;
end
endcase
1'b1: begin
control <= i_data;
end
endcase
end
end
end
@@ -80,7 +83,7 @@ always_comb begin
case (addr)
1'b0: begin
o_data = rx_data;
end
end
1'b1: begin
o_data = status;

2
hw/efinix_fpga/super6502.xml
View File

@@ -1,4 +1,4 @@
<efx:project xmlns:efx="http://www.efinixinc.com/enf_proj" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" name="super6502" description="" last_change_date="Mon Sep 18 2023 07:52:10 PM" location="/home/byron/ServerProjects/super6502/hw/efinix_fpga" sw_version="2023.1.150" last_run_state="pass" last_run_tool="efx_pgm" last_run_flow="bitstream" config_result_in_sync="sync" design_ood="sync" place_ood="sync" route_ood="sync" xsi:schemaLocation="http://www.efinixinc.com/enf_proj enf_proj.xsd">
<efx:project xmlns:efx="http://www.efinixinc.com/enf_proj" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" name="super6502" description="" last_change_date="Wed Sep 27 2023 10:59:23 PM" location="/home/byron/Projects/super6502/hw/efinix_fpga" sw_version="2023.1.150" last_run_state="pass" last_run_tool="efx_pgm" last_run_flow="bitstream" config_result_in_sync="sync" design_ood="sync" place_ood="sync" route_ood="sync" xsi:schemaLocation="http://www.efinixinc.com/enf_proj enf_proj.xsd">
<efx:device_info>
<efx:family name="Trion" />
<efx:device name="T20F256" />

10
sw/bios/boot2.s
View File

@@ -335,10 +335,10 @@ _start:
@end: bra @end
str: .asciiz "boot2\r\n"
str: .asciiz "boot2\n"
kernel_str: .asciiz "KERNEL O65"
_good: .asciiz "Found KERNEL\r\n"
word_str: .asciiz "Word Value: %x\r\n"
_good: .asciiz "Found KERNEL\n"
word_str: .asciiz "Word Value: %x\n"
opt_str: .asciiz "Opt Len: %x, Opt Type: %x\r\n"
opt_done: .asciiz "Options done. total option length: %x\r\n"
opt_str: .asciiz "Opt Len: %x, Opt Type: %x\n"
opt_done: .asciiz "Options done. total option length: %x\n"

10
sw/bios/bootloader.s
View File

@@ -173,12 +173,12 @@ _main:
@end: bra @end
str: .asciiz "boot\r\n"
str: .asciiz "boot\n"
_boot2_str: .asciiz "BOOT2 BIN"
_fail: .asciiz "not bootloader\r\n"
_good: .asciiz "found bootloader!\r\n"
_cluster: .asciiz "cluster: %lx\r\n"
_addr: .asciiz "addr: %x\r\n"
_fail: .asciiz "not bootloader\n"
_good: .asciiz "found bootloader!\n"
_cluster: .asciiz "cluster: %lx\n"
_addr: .asciiz "addr: %x\n"
_end:
.res (440+_start-_end)

8
sw/bios/devices/sd_card.c
View File

@@ -20,7 +20,7 @@ uint8_t SD_init()
cmdAttempts++;
if(cmdAttempts == CMD0_MAX_ATTEMPTS)
{
cputs("Go IDLE\r\n");
cputs("Go IDLE\n");
return SD_ERROR;
}
}
@@ -30,7 +30,7 @@ uint8_t SD_init()
SD_sendIfCond(res);
if(res[0] != SD_IN_IDLE_STATE)
{
cputs("IF Cond\r\n");
cputs("IF Cond\n");
return SD_ERROR;
}
@@ -44,7 +44,7 @@ uint8_t SD_init()
{
if(cmdAttempts == CMD55_MAX_ATTEMPTS)
{
cputs("op_cond error\r\n");
cputs("op_cond error\n");
return SD_ERROR;
}
@@ -304,7 +304,7 @@ void SD_sendStatus(uint8_t *res)
// while(++readAttempts != SD_MAX_READ_ATTEMPTS)
// if((read = spi_exchange(0xFF)) != 0xFF) break;
// cprintf("read attempts: %d\r\n", readAttempts);
// cprintf("read attempts: %d\n", readAttempts);
// // if response token is 0xFE
// if(read == SD_START_TOKEN)

4
sw/bios/devices/sd_print.c
View File

@@ -13,7 +13,7 @@ void SD_printBuf(uint8_t *buf)
cprintf("%2x", *buf++);
if(colCount == 31)
{
cputs("\r\n");
cputs("\n");
colCount = 0;
}
else
@@ -22,5 +22,5 @@ void SD_printBuf(uint8_t *buf)
colCount++;
}
}
cputs("\r\n");
cputs("\n");
}

10
sw/bios/main.c
View File

@@ -19,16 +19,16 @@ int main() {
uint32_t addr = 0x00000000;
uint16_t i;
cputs("Start\r\n");
cputs("Start\n");
// initialize sd card
if(SD_init() != SD_SUCCESS)
{
cputs("Error\r\n");
cputs("Error\n");
}
else
{
cputs("Success\r\n");
cputs("Success\n");
res[0] = SD_readSingleBlock(addr, buf, &token);
@@ -38,9 +38,9 @@ int main() {
//else if error token received, print
else if(!(token & 0xF0))
{
cputs("Error\r\n");
cputs("Error\n");
} else {
cprintf("bad token: %x\r\n", token);
cprintf("bad token: %x\n", token);
}
__asm__ ("jmp (%v)", buf);

2
sw/kernel/kernel.c
View File

@@ -16,7 +16,7 @@ int main() {
cprintf("%s", string);
cprintf("Here is a long string: %s\r\n", longstring);
cprintf("Here is a long string: %s\n", longstring);
while(1);