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Update IP

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This commit is contained in:
Byron Lathi
2023-07-19 21:06:20 -07:00
parent 2f11808f11
commit 21e3a477c1
26 changed files with 1804 additions and 4334 deletions
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hw/efinix_fpga/ip/uart/ipm/component.pickle Normal file
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hw/efinix_fpga/ip/uart/ipm/graph.pickle Normal file
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35
hw/efinix_fpga/ip/uart/settings.json
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@@ -9,26 +9,41 @@
"vendor": "efinixinc.com",
"library": "serial_interface",
"name": "efx_uart",
"version": "2.0"
"version": "5.0"
}
],
"conf": {
"BYTE": "1",
"CLOCK_FREQ": "50000000",
"BAUD": "115200",
"ENABLE_PARITY": "0",
"FIX_BAUDRATE": "1",
"PARITY_MODE": "0",
"BOOTUP_CHECK": "0"
"ENABLE_PARITY": "1'b0",
"FIX_BAUDRATE": "1'b1",
"PARITY_MODE": "1'b0",
"BOOTUP_CHECK": "1'b1"
},
"output": {
"external_source_source": [
"/home/byron/Projects/super6502/hw/efinix_fpga/ip/uart/uart.v",
"/home/byron/Projects/super6502/hw/efinix_fpga/ip/uart/uart_define.vh",
"/home/byron/Projects/super6502/hw/efinix_fpga/ip/uart/uart_tmpl.vhd",
"/home/byron/Projects/super6502/hw/efinix_fpga/ip/uart/uart_tmpl.v"
"/home/byron/Projects/super6502/hw/efinix_fpga/ip/uart/uart_tmpl.v",
"/home/byron/Projects/super6502/hw/efinix_fpga/ip/uart/uart.v",
"/home/byron/Projects/super6502/hw/efinix_fpga/ip/uart/uart_tmpl.vhd"
],
"external_example_example": [
"/home/byron/Projects/super6502/hw/efinix_fpga/ip/uart/T20F256_devkit/command_state.v",
"/home/byron/Projects/super6502/hw/efinix_fpga/ip/uart/T20F256_devkit/decoder.v",
"/home/byron/Projects/super6502/hw/efinix_fpga/ip/uart/T20F256_devkit/encoder.v",
"/home/byron/Projects/super6502/hw/efinix_fpga/ip/uart/T20F256_devkit/led_ctl.v",
"/home/byron/Projects/super6502/hw/efinix_fpga/ip/uart/T20F256_devkit/resets.v",
"/home/byron/Projects/super6502/hw/efinix_fpga/ip/uart/T20F256_devkit/uart_defines.v",
"/home/byron/Projects/super6502/hw/efinix_fpga/ip/uart/T20F256_devkit/uart_demo_top.v",
"/home/byron/Projects/super6502/hw/efinix_fpga/ip/uart/T20F256_devkit/user_register.v",
"/home/byron/Projects/super6502/hw/efinix_fpga/ip/uart/T20F256_devkit/uart_demo.peri.xml",
"/home/byron/Projects/super6502/hw/efinix_fpga/ip/uart/T20F256_devkit/uart_demo.xml",
"/home/byron/Projects/super6502/hw/efinix_fpga/ip/uart/T20F256_devkit/uart_timing_T20.sdc",
"/home/byron/Projects/super6502/hw/efinix_fpga/ip/uart/T20F256_devkit/uart.v",
"/home/byron/Projects/super6502/hw/efinix_fpga/ip/uart/T20F256_devkit/uart_define.vh"
]
},
"sw_version": "2022.2.322",
"generated_date": "2023-01-12T01:01:22.177819"
"sw_version": "2023.1.150",
"generated_date": "2023-07-16T20:20:12.259229"
}

24
hw/efinix_fpga/ip/uart/uart.v
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@@ -1,11 +1,11 @@
// =============================================================================
// Generated by efx_ipmgr
// Version: 2022.2.322
// IP Version: 2.0
// Version: 2023.1.150
// IP Version: 5.0
// =============================================================================
////////////////////////////////////////////////////////////////////////////////
// Copyright (C) 2013-2022 Efinix Inc. All rights reserved.
// Copyright (C) 2013-2023 Efinix Inc. All rights reserved.
//
// This document contains proprietary information which is
// protected by copyright. All rights are reserved. This notice
@@ -43,7 +43,7 @@
//
////////////////////////////////////////////////////////////////////////////////
`define IP_UUID _5423258f8d324e3e81f7da25952c84a2
`define IP_UUID _d1961caf8b8d4ca092806671a99095c2
`define IP_NAME_CONCAT(a,b) a``b
`define IP_MODULE_NAME(name) `IP_NAME_CONCAT(name,`IP_UUID)
module uart (
@@ -58,18 +58,18 @@ output rx_busy,
output baud_x16_ce,
input clk,
input reset,
input [7:0] tx_data,
input [2:0] baud_rate,
input tx_en
input tx_en,
input [7:0] tx_data
);
`IP_MODULE_NAME(top_uart) #(
.BYTE (1),
.CLOCK_FREQ (50000000),
.BAUD (115200),
.ENABLE_PARITY (0),
.FIX_BAUDRATE (1),
.PARITY_MODE (0),
.BOOTUP_CHECK (0)
.ENABLE_PARITY (1'b0),
.FIX_BAUDRATE (1'b1),
.PARITY_MODE (1'b0),
.BOOTUP_CHECK (1'b1)
) u_top_uart(
.tx_o ( tx_o ),
.rx_i ( rx_i ),
@@ -82,9 +82,9 @@ input tx_en
.baud_x16_ce ( baud_x16_ce ),
.clk ( clk ),
.reset ( reset ),
.tx_data ( tx_data ),
.baud_rate ( baud_rate ),
.tx_en ( tx_en )
.tx_en ( tx_en ),
.tx_data ( tx_data )
);
endmodule

14
hw/efinix_fpga/ip/uart/uart_define.vh
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@@ -1,11 +1,11 @@
// =============================================================================
// Generated by efx_ipmgr
// Version: 2022.2.322
// IP Version: 2.0
// Version: 2023.1.150
// IP Version: 5.0
// =============================================================================
////////////////////////////////////////////////////////////////////////////////
// Copyright (C) 2013-2022 Efinix Inc. All rights reserved.
// Copyright (C) 2013-2023 Efinix Inc. All rights reserved.
//
// This document contains proprietary information which is
// protected by copyright. All rights are reserved. This notice
@@ -46,7 +46,7 @@
localparam BYTE = 1;
localparam CLOCK_FREQ = 50000000;
localparam BAUD = 115200;
localparam ENABLE_PARITY = 0;
localparam FIX_BAUDRATE = 1;
localparam PARITY_MODE = 0;
localparam BOOTUP_CHECK = 0;
localparam ENABLE_PARITY = 1'b0;
localparam FIX_BAUDRATE = 1'b1;
localparam PARITY_MODE = 1'b0;
localparam BOOTUP_CHECK = 1'b1;

6
hw/efinix_fpga/ip/uart/uart_tmpl.v
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@@ -1,5 +1,5 @@
////////////////////////////////////////////////////////////////////////////////
// Copyright (C) 2013-2022 Efinix Inc. All rights reserved.
// Copyright (C) 2013-2023 Efinix Inc. All rights reserved.
//
// This document contains proprietary information which is
// protected by copyright. All rights are reserved. This notice
@@ -49,7 +49,7 @@ uart u_uart(
.baud_x16_ce ( baud_x16_ce ),
.clk ( clk ),
.reset ( reset ),
.tx_data ( tx_data ),
.baud_rate ( baud_rate ),
.tx_en ( tx_en )
.tx_en ( tx_en ),
.tx_data ( tx_data )
);

84
hw/efinix_fpga/ip/uart/uart_tmpl.vhd
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@@ -1,41 +1,41 @@
////////////////////////////////////////////////////////////////////////////////
// Copyright (C) 2013-2022 Efinix Inc. All rights reserved.
//
// This document contains proprietary information which is
// protected by copyright. All rights are reserved. This notice
// refers to original work by Efinix, Inc. which may be derivitive
// of other work distributed under license of the authors. In the
// case of derivative work, nothing in this notice overrides the
// original author's license agreement. Where applicable, the
// original license agreement is included in it's original
// unmodified form immediately below this header.
//
// WARRANTY DISCLAIMER.
// THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND
// EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH
// RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES,
// INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF
// MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR
// PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED
// WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE.
//
// LIMITATION OF LIABILITY.
// NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY
// INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT
// MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY
// OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT,
// SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY
// CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF
// GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR
// MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN
// THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER
// (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE
// BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO
// NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR
// CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT
// APPLY TO LICENSEE.
//
////////////////////////////////////////////////////////////////////////////////
--------------------------------------------------------------------------------
-- Copyright (C) 2013-2023 Efinix Inc. All rights reserved.
--
-- This document contains proprietary information which is
-- protected by copyright. All rights are reserved. This notice
-- refers to original work by Efinix, Inc. which may be derivitive
-- of other work distributed under license of the authors. In the
-- case of derivative work, nothing in this notice overrides the
-- original author's license agreement. Where applicable, the
-- original license agreement is included in it's original
-- unmodified form immediately below this header.
--
-- WARRANTY DISCLAIMER.
-- THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND
-- EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH
-- RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES,
-- INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF
-- MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR
-- PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED
-- WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE.
--
-- LIMITATION OF LIABILITY.
-- NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY
-- INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT
-- MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY
-- OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT,
-- SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY
-- CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF
-- GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR
-- MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN
-- THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER
-- (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE
-- BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO
-- NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR
-- CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT
-- APPLY TO LICENSEE.
--
--------------------------------------------------------------------------------
------------- Begin Cut here for COMPONENT Declaration ------
COMPONENT uart is
PORT (
@@ -50,9 +50,9 @@ rx_busy : out std_logic;
baud_x16_ce : out std_logic;
clk : in std_logic;
reset : in std_logic;
tx_data : in std_logic_vector(7 downto 0);
baud_rate : in std_logic_vector(2 downto 0);
tx_en : in std_logic);
tx_en : in std_logic;
tx_data : in std_logic_vector(7 downto 0));
END COMPONENT;
---------------------- End COMPONENT Declaration ------------
@@ -70,7 +70,7 @@ rx_busy => rx_busy,
baud_x16_ce => baud_x16_ce,
clk => clk,
reset => reset,
tx_data => tx_data,
baud_rate => baud_rate,
tx_en => tx_en);
tx_en => tx_en,
tx_data => tx_data);
------------------------ End INSTANTIATION Template ---------