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Synthesize sd card dma

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This commit is contained in:
Byron Lathi
2024-03-17 22:26:42 -07:00
parent 9b50dab855
commit 25f51deaa7
6 changed files with 148 additions and 108 deletions
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1
hw/super6502_fpga/sources.list
View File

@@ -21,3 +21,4 @@ src/sub/sd_controller/src/sd_command.sv
src/sub/sd_controller/src/sd_control.sv
src/sub/sd_controller/src/sd_controller_top.sv
src/sub/sd_controller/src/sd_data.sv
src/sub/sd_controller/src/sd_dma.sv

56
hw/super6502_fpga/src/rtl/super_6502_fpga.sv
View File

@@ -236,29 +236,29 @@ cpu_wrapper u_cpu_wrapper_0(
axi_crossbar #(
.N_INITIATORS(1),
.N_INITIATORS(2),
.N_TARGETS(4)
) u_crossbar (
.clk(i_sysclk),
.rst(~master_reset),
.ini_araddr ({cpu0_ARADDR }),
.ini_arvalid ({cpu0_ARVALID }),
.ini_arready ({cpu0_ARREADY }),
.ini_rdata ({cpu0_RDATA }),
.ini_rresp ({cpu0_RRESP }),
.ini_rvalid ({cpu0_RVALID }),
.ini_rready ({cpu0_RREADY }),
.ini_awaddr ({cpu0_AWADDR }),
.ini_awready ({cpu0_AWREADY }),
.ini_awvalid ({cpu0_AWVALID }),
.ini_wvalid ({cpu0_WVALID }),
.ini_wready ({cpu0_WREADY }),
.ini_wdata ({cpu0_WDATA }),
.ini_wstrb ({cpu0_WSTRB }),
.ini_bresp ({cpu0_BRESP }),
.ini_bvalid ({cpu0_BVALID }),
.ini_bready ({cpu0_BREADY }),
.ini_araddr ({cpu0_ARADDR, sd_controller_dma_ARADDR }),
.ini_arvalid ({cpu0_ARVALID, sd_controller_dma_ARVALID }),
.ini_arready ({cpu0_ARREADY, sd_controller_dma_ARREADY }),
.ini_rdata ({cpu0_RDATA, sd_controller_dma_RDATA }),
.ini_rresp ({cpu0_RRESP, sd_controller_dma_RRESP }),
.ini_rvalid ({cpu0_RVALID, sd_controller_dma_RVALID }),
.ini_rready ({cpu0_RREADY, sd_controller_dma_RREADY }),
.ini_awaddr ({cpu0_AWADDR, sd_controller_dma_AWADDR }),
.ini_awready ({cpu0_AWREADY, sd_controller_dma_AWREADY }),
.ini_awvalid ({cpu0_AWVALID, sd_controller_dma_AWVALID }),
.ini_wvalid ({cpu0_WVALID, sd_controller_dma_WVALID }),
.ini_wready ({cpu0_WREADY, sd_controller_dma_WREADY }),
.ini_wdata ({cpu0_WDATA, sd_controller_dma_WDATA }),
.ini_wstrb ({cpu0_WSTRB, sd_controller_dma_WSTRB }),
.ini_bresp ({cpu0_BRESP, sd_controller_dma_BRESP }),
.ini_bvalid ({cpu0_BVALID, sd_controller_dma_BVALID }),
.ini_bready ({cpu0_BREADY, sd_controller_dma_BREADY }),
.tgt_araddr ({ram_araddr, rom_araddr, sdram_ARADDR, sd_controller_csr_ARADDR }),
.tgt_arvalid ({ram_arvalid, rom_arvalid, sdram_ARVALID, sd_controller_csr_ARVALID }),
.tgt_arready ({ram_arready, rom_arready, sdram_ARREADY, sd_controller_csr_ARREADY }),
@@ -479,6 +479,26 @@ sd_controller_top u_sd_controller (
.s_apb_prdata(sd_controller_apb_prdata),
.s_apb_pslverr(sd_controller_apb_pslverr),
.o_AWVALID (sd_controller_dma_AWVALID),
.i_AWREADY (sd_controller_dma_AWREADY),
.o_AWADDR (sd_controller_dma_AWADDR),
.o_WVALID (sd_controller_dma_WVALID),
.i_WREADY (sd_controller_dma_WREADY),
.o_WDATA (sd_controller_dma_WDATA),
.o_WSTRB (sd_controller_dma_WSTRB),
.i_BVALID (sd_controller_dma_BVALID),
.o_BREADY (sd_controller_dma_BREADY),
.i_BRESP (sd_controller_dma_BRESP),
.o_ARVALID (sd_controller_dma_ARVALID),
.i_ARREADY (sd_controller_dma_ARREADY),
.o_ARADDR (sd_controller_dma_ARADDR),
.i_RVALID (sd_controller_dma_RVALID),
.o_RREADY (sd_controller_dma_RREADY),
.i_RDATA (sd_controller_dma_RDATA),
.i_RRESP (sd_controller_dma_RRESP),
.i_sd_cmd(i_sd_cmd),
.o_sd_cmd(o_sd_cmd),
.o_sd_cmd_oe(o_sd_cmd_oe),

2
hw/super6502_fpga/src/sub/rtl-common

Submodule hw/super6502_fpga/src/sub/rtl-common updated: bdf655b77b...401042bb0f

2
hw/super6502_fpga/src/sub/sd_controller

Submodule hw/super6502_fpga/src/sub/sd_controller updated: 52665b1b89...a16ffb427c

4
hw/super6502_fpga/super6502_fpga.xml
View File

@@ -1,5 +1,4 @@
<?xml version="1.0" encoding="UTF-8"?>
<efx:project name="super6502_fpga" description="" last_change_date="Tue March 12 2024 19:59:12" location="/home/byron/Projects/super6502/hw/super6502_fpga" sw_version="2023.1.150" last_run_state="pass" last_run_tool="efx_pgm" last_run_flow="bitstream" config_result_in_sync="sync" design_ood="sync" place_ood="sync" route_ood="sync" xmlns:efx="http://www.efinixinc.com/enf_proj" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:schemaLocation="http://www.efinixinc.com/enf_proj enf_proj.xsd">
<efx:project xmlns:efx="http://www.efinixinc.com/enf_proj" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" name="super6502_fpga" description="" last_change_date="Sun Mar 17 2024 10:14:03 PM" location="/home/byron/Projects/super6502/hw/super6502_fpga" sw_version="2023.1.150" last_run_state="pass" last_run_tool="efx_pgm" last_run_flow="bitstream" config_result_in_sync="sync" design_ood="sync" place_ood="sync" route_ood="sync" xsi:schemaLocation="http://www.efinixinc.com/enf_proj enf_proj.xsd">
<efx:device_info>
<efx:family name="Trion" />
<efx:device name="T20F256" />
@@ -23,6 +22,7 @@
<efx:design_file name="src/sub/sd_controller/src/sd_control.sv" version="default" library="default" />
<efx:design_file name="src/sub/sd_controller/src/sd_controller_top.sv" version="default" library="default" />
<efx:design_file name="src/sub/sd_controller/src/sd_command.sv" version="default" library="default" />
<efx:design_file name="src/sub/sd_controller/src/sd_dma.sv" version="default" library="default" />
<efx:design_file name="src/sub/sd_controller/src/regs/sd_controller_regs.sv" version="default" library="default" />
<efx:design_file name="src/sub/sd_controller/src/regs/sd_controller_regs_pkg.sv" version="default" library="default" />
<efx:design_file name="src/sub/sd_controller/src/sd_data.sv" version="default" library="default" />

19
sw/test_code/sd_controller_test/main.s
View File

@@ -11,6 +11,9 @@ SD_ARG = SD_CONTROLLER + $4
SD_RESP = SD_CONTROLLER + $10
CLK_DIV = $20
SD_DMA_BASE = SD_CONTROLLER + $28
SD_DMA_STAT_CTRL = SD_CONTROLLER + $2C
.zeropage
rca: .res 4
@@ -107,6 +110,22 @@ card_ready:
lda #17
sta SD_CONTROLLER
lda #$10
sta SD_DMA_BASE + 1
lda #1
sta SD_DMA_STAT_CTRL
@poll: lda SD_DMA_STAT_CTRL+2
cmp #$1
bne @poll
stz SD_DMA_STAT_CTRL
lda $1000
lda $1001
lda $1002
lda $1003
@end: bra @end
delay: