Update submodules, update sources

hw/super6502_fpga/src/sim/hvl/sim_top.sv

@@ -168,7 +168,9 @@ sd_card_emu u_sd_card_emu(
     .clk(o_sd_clk),
     .rst(~button_reset),
     .i_cmd(o_sd_cmd),
-    .o_cmd(i_sd_cmd)
+    .o_cmd(i_sd_cmd),
+    .i_dat(o_sd_dat),
+    .o_dat(i_sd_dat)
 );
 
 initial begin

hw/super6502_fpga/src/sim/sources.list

@@ -4,4 +4,5 @@ sub/verilog-6502/cpu_65c02.v
 sub/sim_sdram/generic_sdr.v
 sub/verilog-sd-emulator/src/sd_card_command.sv
 sub/verilog-sd-emulator/src/sd_card_emu.sv
-sub/verilog-sd-emulator/src/sd_card_state_controller.sv
+sub/verilog-sd-emulator/src/sd_card_state_controller.sv
+sub/verilog-sd-emulator/src/sd_card_data.sv