Merge branch '10-interrupt-controller' into 'master'
Resolve "Interrupt Controller" Closes #10 See merge request bslathi19/super6502!39
This commit is contained in:
Byron Lathi
@@ -145,4 +145,19 @@ mapper_code sim:
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- cd hw/efinix_fpga/simulation
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- cd hw/efinix_fpga/simulation
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- make clean
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- make clean
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- TEST_PROGRAM_NAME=mapper_test make mapper_code_tb
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- TEST_PROGRAM_NAME=mapper_test make mapper_code_tb
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- ./mapper_code_tb
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- ./mapper_code_tb
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interrupt_controller sim:
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tags:
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- linux
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- iverilog
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stage: simulate
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artifacts:
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paths:
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- hw/efinix_fpga/simulation/interrupt_controller.vcd
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script:
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- source init_env.sh
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- cd hw/efinix_fpga/simulation
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- make clean
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- TEST_PROGRAM_NAME=mapper_test make interrupt_controller_tb
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- ./interrupt_controller_tb
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405
doc/pic.drawio
Normal file
405
doc/pic.drawio
Normal file
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</mxCell>
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<mxGeometry relative="1" as="geometry" />
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</mxCell>
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<mxGeometry relative="1" as="geometry" />
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</mxCell>
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<mxCell id="3cJaNxErLRnUAumjy6m_-90" value="data_in mux" style="shape=trapezoid;perimeter=trapezoidPerimeter;whiteSpace=wrap;html=1;fixedSize=1;rotation=-90;" vertex="1" parent="1">
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|
<mxGeometry x="15.030000000000015" y="119.74000000000001" width="120" height="60" as="geometry" />
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</mxCell>
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<mxCell id="3cJaNxErLRnUAumjy6m_-91" value="" style="shape=flexArrow;endArrow=classic;html=1;rounded=0;entryX=0.5;entryY=0;entryDx=0;entryDy=0;" edge="1" parent="1" target="3cJaNxErLRnUAumjy6m_-90">
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<mxGeometry width="50" height="50" relative="1" as="geometry">
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<mxPoint x="-34.969999999999985" y="149.74" as="sourcePoint" />
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<mxPoint x="-24.969999999999985" y="109.74000000000001" as="targetPoint" />
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</mxGeometry>
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</mxCell>
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<mxPoint x="-49" y="-1" as="offset" />
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</mxGeometry>
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</mxCell>
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<mxCell id="3cJaNxErLRnUAumjy6m_-93" value="" style="endArrow=classic;html=1;rounded=0;entryX=1;entryY=0.5;entryDx=0;entryDy=0;" edge="1" parent="1" target="3cJaNxErLRnUAumjy6m_-90">
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<mxGeometry width="50" height="50" relative="1" as="geometry">
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<mxPoint x="75.03000000000002" y="39.739999999999995" as="sourcePoint" />
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<mxPoint x="85.03000000000002" y="-10.260000000000005" as="targetPoint" />
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</mxGeometry>
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</mxCell>
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|
<mxCell id="3cJaNxErLRnUAumjy6m_-94" value="addr" style="edgeLabel;html=1;align=center;verticalAlign=middle;resizable=0;points=[];" vertex="1" connectable="0" parent="3cJaNxErLRnUAumjy6m_-93">
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<mxGeometry x="-0.8263" y="1" relative="1" as="geometry">
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<mxPoint x="-1" y="-15" as="offset" />
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</mxGeometry>
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</mxCell>
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<mxCell id="3cJaNxErLRnUAumjy6m_-100" value="" style="edgeStyle=orthogonalEdgeStyle;rounded=0;orthogonalLoop=1;jettySize=auto;html=1;" edge="1" parent="1" source="3cJaNxErLRnUAumjy6m_-96" target="3cJaNxErLRnUAumjy6m_-99">
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|
<mxGeometry relative="1" as="geometry" />
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|
</mxCell>
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|
<mxCell id="3cJaNxErLRnUAumjy6m_-105" style="edgeStyle=orthogonalEdgeStyle;rounded=0;orthogonalLoop=1;jettySize=auto;html=1;entryX=0;entryY=0.5;entryDx=0;entryDy=0;" edge="1" parent="1" source="3cJaNxErLRnUAumjy6m_-96" target="3cJaNxErLRnUAumjy6m_-102">
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|
<mxGeometry relative="1" as="geometry">
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|
<Array as="points">
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|
<mxPoint x="245" y="160" />
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|
<mxPoint x="840" y="160" />
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|
</Array>
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|
</mxGeometry>
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|
</mxCell>
|
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|
<mxCell id="3cJaNxErLRnUAumjy6m_-112" value="" style="edgeStyle=orthogonalEdgeStyle;rounded=0;orthogonalLoop=1;jettySize=auto;html=1;" edge="1" parent="1" source="3cJaNxErLRnUAumjy6m_-96" target="3cJaNxErLRnUAumjy6m_-109">
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<mxGeometry relative="1" as="geometry" />
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|
</mxCell>
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|
<mxCell id="3cJaNxErLRnUAumjy6m_-118" value="cmd=EOI" style="edgeLabel;html=1;align=center;verticalAlign=middle;resizable=0;points=[];" vertex="1" connectable="0" parent="3cJaNxErLRnUAumjy6m_-112">
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<mxGeometry x="-0.2899" relative="1" as="geometry">
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<mxPoint x="16" y="-20" as="offset" />
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</mxGeometry>
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</mxCell>
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<mxCell id="3cJaNxErLRnUAumjy6m_-120" style="edgeStyle=orthogonalEdgeStyle;rounded=0;orthogonalLoop=1;jettySize=auto;html=1;exitX=0.25;exitY=1;exitDx=0;exitDy=0;entryX=0.5;entryY=0;entryDx=0;entryDy=0;" edge="1" parent="1" source="3cJaNxErLRnUAumjy6m_-96" target="3cJaNxErLRnUAumjy6m_-38">
|
||||||
|
<mxGeometry relative="1" as="geometry">
|
||||||
|
<Array as="points">
|
||||||
|
<mxPoint x="215" y="160" />
|
||||||
|
<mxPoint x="120" y="160" />
|
||||||
|
</Array>
|
||||||
|
</mxGeometry>
|
||||||
|
</mxCell>
|
||||||
|
<mxCell id="3cJaNxErLRnUAumjy6m_-121" style="edgeStyle=orthogonalEdgeStyle;rounded=0;orthogonalLoop=1;jettySize=auto;html=1;exitX=0.25;exitY=1;exitDx=0;exitDy=0;entryX=0.5;entryY=0;entryDx=0;entryDy=0;" edge="1" parent="1" source="3cJaNxErLRnUAumjy6m_-96" target="3cJaNxErLRnUAumjy6m_-11">
|
||||||
|
<mxGeometry relative="1" as="geometry">
|
||||||
|
<Array as="points">
|
||||||
|
<mxPoint x="215" y="160" />
|
||||||
|
<mxPoint x="120" y="160" />
|
||||||
|
<mxPoint x="120" y="370" />
|
||||||
|
<mxPoint x="240" y="370" />
|
||||||
|
</Array>
|
||||||
|
</mxGeometry>
|
||||||
|
</mxCell>
|
||||||
|
<mxCell id="3cJaNxErLRnUAumjy6m_-122" style="edgeStyle=orthogonalEdgeStyle;rounded=0;orthogonalLoop=1;jettySize=auto;html=1;exitX=0.25;exitY=1;exitDx=0;exitDy=0;entryX=0.5;entryY=0;entryDx=0;entryDy=0;" edge="1" parent="1" source="3cJaNxErLRnUAumjy6m_-96" target="3cJaNxErLRnUAumjy6m_-12">
|
||||||
|
<mxGeometry relative="1" as="geometry">
|
||||||
|
<Array as="points">
|
||||||
|
<mxPoint x="215" y="160" />
|
||||||
|
<mxPoint x="120" y="160" />
|
||||||
|
<mxPoint x="120" y="370" />
|
||||||
|
<mxPoint x="360" y="370" />
|
||||||
|
</Array>
|
||||||
|
</mxGeometry>
|
||||||
|
</mxCell>
|
||||||
|
<mxCell id="3cJaNxErLRnUAumjy6m_-123" value="byte_en" style="edgeLabel;html=1;align=center;verticalAlign=middle;resizable=0;points=[];" vertex="1" connectable="0" parent="3cJaNxErLRnUAumjy6m_-122">
|
||||||
|
<mxGeometry x="-0.7727" relative="1" as="geometry">
|
||||||
|
<mxPoint y="-10" as="offset" />
|
||||||
|
</mxGeometry>
|
||||||
|
</mxCell>
|
||||||
|
<mxCell id="3cJaNxErLRnUAumjy6m_-96" value="CMD register" style="rounded=0;whiteSpace=wrap;html=1;" vertex="1" parent="1">
|
||||||
|
<mxGeometry x="185.03000000000003" y="89.74000000000001" width="120" height="60" as="geometry" />
|
||||||
|
</mxCell>
|
||||||
|
<mxCell id="3cJaNxErLRnUAumjy6m_-99" value="data_sel_mux" style="shape=trapezoid;perimeter=trapezoidPerimeter;whiteSpace=wrap;html=1;fixedSize=1;rotation=-90;" vertex="1" parent="1">
|
||||||
|
<mxGeometry x="185.03" y="200" width="120" height="60" as="geometry" />
|
||||||
|
</mxCell>
|
||||||
|
<mxCell id="3cJaNxErLRnUAumjy6m_-106" style="edgeStyle=orthogonalEdgeStyle;rounded=0;orthogonalLoop=1;jettySize=auto;html=1;exitX=0.5;exitY=0;exitDx=0;exitDy=0;shape=flexArrow;" edge="1" parent="1" source="3cJaNxErLRnUAumjy6m_-102">
|
||||||
|
<mxGeometry relative="1" as="geometry">
|
||||||
|
<mxPoint x="920" y="499.85185185185173" as="targetPoint" />
|
||||||
|
</mxGeometry>
|
||||||
|
</mxCell>
|
||||||
|
<mxCell id="3cJaNxErLRnUAumjy6m_-107" value="data_out" style="edgeLabel;html=1;align=center;verticalAlign=middle;resizable=0;points=[];" vertex="1" connectable="0" parent="3cJaNxErLRnUAumjy6m_-106">
|
||||||
|
<mxGeometry x="0.3413" y="-9" relative="1" as="geometry">
|
||||||
|
<mxPoint y="-39" as="offset" />
|
||||||
|
</mxGeometry>
|
||||||
|
</mxCell>
|
||||||
|
<mxCell id="3cJaNxErLRnUAumjy6m_-102" value="" style="shape=trapezoid;perimeter=trapezoidPerimeter;whiteSpace=wrap;html=1;fixedSize=1;rotation=90;" vertex="1" parent="1">
|
||||||
|
<mxGeometry x="780" y="470" width="120" height="60" as="geometry" />
|
||||||
|
</mxCell>
|
||||||
|
<mxCell id="3cJaNxErLRnUAumjy6m_-114" style="edgeStyle=orthogonalEdgeStyle;rounded=0;orthogonalLoop=1;jettySize=auto;html=1;shape=flexArrow;" edge="1" parent="1" source="3cJaNxErLRnUAumjy6m_-109" target="3cJaNxErLRnUAumjy6m_-113">
|
||||||
|
<mxGeometry relative="1" as="geometry" />
|
||||||
|
</mxCell>
|
||||||
|
<mxCell id="3cJaNxErLRnUAumjy6m_-109" value="EOI shifter" style="ellipse;whiteSpace=wrap;html=1;" vertex="1" parent="1">
|
||||||
|
<mxGeometry x="360" y="90" width="90" height="59.74" as="geometry" />
|
||||||
|
</mxCell>
|
||||||
|
<mxCell id="3cJaNxErLRnUAumjy6m_-115" style="edgeStyle=orthogonalEdgeStyle;rounded=0;orthogonalLoop=1;jettySize=auto;html=1;entryX=0.75;entryY=0;entryDx=0;entryDy=0;shape=flexArrow;" edge="1" parent="1" source="3cJaNxErLRnUAumjy6m_-113" target="3cJaNxErLRnUAumjy6m_-12">
|
||||||
|
<mxGeometry relative="1" as="geometry">
|
||||||
|
<Array as="points">
|
||||||
|
<mxPoint x="365" y="360" />
|
||||||
|
<mxPoint x="380" y="360" />
|
||||||
|
</Array>
|
||||||
|
</mxGeometry>
|
||||||
|
</mxCell>
|
||||||
|
<mxCell id="3cJaNxErLRnUAumjy6m_-113" value="&amp;" style="ellipse;whiteSpace=wrap;html=1;aspect=fixed;" vertex="1" parent="1">
|
||||||
|
<mxGeometry x="340" y="280" width="50" height="50" as="geometry" />
|
||||||
|
</mxCell>
|
||||||
|
<mxCell id="3cJaNxErLRnUAumjy6m_-116" value="" style="shape=flexArrow;endArrow=classic;html=1;rounded=0;entryX=1;entryY=0.5;entryDx=0;entryDy=0;exitX=1;exitY=0.138;exitDx=0;exitDy=0;exitPerimeter=0;" edge="1" parent="1" source="3cJaNxErLRnUAumjy6m_-12" target="3cJaNxErLRnUAumjy6m_-113">
|
||||||
|
<mxGeometry width="50" height="50" relative="1" as="geometry">
|
||||||
|
<mxPoint x="410" y="452" as="sourcePoint" />
|
||||||
|
<mxPoint x="460" y="330" as="targetPoint" />
|
||||||
|
<Array as="points">
|
||||||
|
<mxPoint x="420" y="452" />
|
||||||
|
<mxPoint x="420" y="305" />
|
||||||
|
</Array>
|
||||||
|
</mxGeometry>
|
||||||
|
</mxCell>
|
||||||
|
<mxCell id="3cJaNxErLRnUAumjy6m_-117" value="<h1>EOI shifter</h1><p>EOI shifter will do 1 &lt;&lt; IRQN&nbsp;<span style="background-color: initial;">and then clear that interrupt in the register</span></p>" style="text;html=1;strokeColor=none;fillColor=none;spacing=5;spacingTop=-20;whiteSpace=wrap;overflow=hidden;rounded=0;" vertex="1" parent="1">
|
||||||
|
<mxGeometry x="420" y="170" width="190" height="120" as="geometry" />
|
||||||
|
</mxCell>
|
||||||
|
<mxCell id="3cJaNxErLRnUAumjy6m_-119" value="<h1>data_sel_mux</h1><p>The upper 3 bits of CMD determine where data goes. The lower 5 bits of cmd determine which of the 32 8 bit registers gets updated. The registers below all of byte enable signals that this is passed to.</p>" style="text;html=1;strokeColor=none;fillColor=none;spacing=5;spacingTop=-20;whiteSpace=wrap;overflow=hidden;rounded=0;" vertex="1" parent="1">
|
||||||
|
<mxGeometry x="-160" y="210" width="220" height="150.26" as="geometry" />
|
||||||
|
</mxCell>
|
||||||
|
</root>
|
||||||
|
</mxGraphModel>
|
||||||
|
</diagram>
|
||||||
|
</mxfile>
|
||||||
@@ -9,6 +9,8 @@ TEST_PROGRAM_NAME?=loop_test
|
|||||||
TEST_FOLDER?=$(REPO_TOP)/sw/test_code/$(TEST_PROGRAM_NAME)
|
TEST_FOLDER?=$(REPO_TOP)/sw/test_code/$(TEST_PROGRAM_NAME)
|
||||||
TEST_PROGRAM?=$(REPO_TOP)/sw/test_code/$(TEST_PROGRAM_NAME)/$(TEST_PROGRAM_NAME).hex
|
TEST_PROGRAM?=$(REPO_TOP)/sw/test_code/$(TEST_PROGRAM_NAME)/$(TEST_PROGRAM_NAME).hex
|
||||||
|
|
||||||
|
STANDALONE_TB= interrupt_controller_tb mapper_code_tb mapper_tb
|
||||||
|
|
||||||
#TODO implement something like sources.list
|
#TODO implement something like sources.list
|
||||||
|
|
||||||
TOP_MODULE=sim_top
|
TOP_MODULE=sim_top
|
||||||
@@ -29,11 +31,11 @@ sim: $(TARGET)
|
|||||||
full_sim: $(TARGET) $(SD_IMAGE)
|
full_sim: $(TARGET) $(SD_IMAGE)
|
||||||
vvp -i $(TARGET) -fst
|
vvp -i $(TARGET) -fst
|
||||||
|
|
||||||
mapper_tb: $(SRCS) $(TBS)
|
$(STANDALONE_TB): $(SRCS) $(TBS)
|
||||||
iverilog -g2005-sv $(FLAGS) -s $@ -o $@ $(INC) $(SRCS) $(TBS)
|
iverilog -g2005-sv $(FLAGS) -s $@ -o $@ $(INC) $(SRCS) $(TBS)
|
||||||
|
|
||||||
mapper_code_tb: $(SRCS) $(TBS) $(INIT_MEM)
|
# mapper_code_tb: $(SRCS) $(TBS) $(INIT_MEM)
|
||||||
iverilog -g2005-sv $(FLAGS) -s $@ -o $@ $(INC) $(SRCS) $(TBS)
|
# iverilog -g2005-sv $(FLAGS) -s $@ -o $@ $(INC) $(SRCS) $(TBS)
|
||||||
|
|
||||||
|
|
||||||
$(TARGET): $(INIT_MEM) $(SRCS)
|
$(TARGET): $(INIT_MEM) $(SRCS)
|
||||||
@@ -55,5 +57,5 @@ clean:
|
|||||||
rm -rf $(TARGET)
|
rm -rf $(TARGET)
|
||||||
rm -rf $(INIT_MEM)
|
rm -rf $(INIT_MEM)
|
||||||
rm -rf $(SD_IMAGE)
|
rm -rf $(SD_IMAGE)
|
||||||
rm -rf mapper_tb
|
rm -rf $(STANDALONE_TB)
|
||||||
rm -rf mapper_tb.vcd
|
rm -rf *.vcd
|
||||||
|
|||||||
208
hw/efinix_fpga/simulation/tbs/interrupt_controller_tb.sv
Normal file
208
hw/efinix_fpga/simulation/tbs/interrupt_controller_tb.sv
Normal file
@@ -0,0 +1,208 @@
|
|||||||
|
`timescale 1ns/1ps
|
||||||
|
|
||||||
|
module interrupt_controller_tb();
|
||||||
|
|
||||||
|
logic r_clk_cpu;
|
||||||
|
|
||||||
|
localparam BITS_256 = 256'hffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff;
|
||||||
|
|
||||||
|
// clk_cpu
|
||||||
|
initial begin
|
||||||
|
r_clk_cpu <= '1;
|
||||||
|
forever begin
|
||||||
|
#125 r_clk_cpu <= ~r_clk_cpu;
|
||||||
|
end
|
||||||
|
end
|
||||||
|
|
||||||
|
logic reset;
|
||||||
|
logic addr;
|
||||||
|
logic [7:0] i_data;
|
||||||
|
logic [7:0] o_data;
|
||||||
|
logic cs;
|
||||||
|
logic rwb;
|
||||||
|
|
||||||
|
logic [255:0] int_in;
|
||||||
|
logic int_out;
|
||||||
|
|
||||||
|
interrupt_controller u_interrupt_controller(
|
||||||
|
.clk(r_clk_cpu),
|
||||||
|
.reset(reset),
|
||||||
|
.i_data(i_data),
|
||||||
|
.o_data(o_data),
|
||||||
|
.addr(addr),
|
||||||
|
.cs(cs),
|
||||||
|
.rwb(rwb),
|
||||||
|
.int_in(int_in),
|
||||||
|
.int_out(int_out)
|
||||||
|
);
|
||||||
|
|
||||||
|
/* Test Level triggered IRQ by triggering IRQ0
|
||||||
|
* and then clearing it,
|
||||||
|
*/
|
||||||
|
task test_edge_irq();
|
||||||
|
$display("Testing Edge IRQ");
|
||||||
|
do_reset();
|
||||||
|
set_enable(255'hff);
|
||||||
|
set_edge_type(255'h0);
|
||||||
|
set_interrupts(1);
|
||||||
|
assert (int_out == 1) else begin
|
||||||
|
errors = errors + 1;
|
||||||
|
$error("Interrupt should be high!");
|
||||||
|
end
|
||||||
|
send_eoi();
|
||||||
|
assert (int_out == 0) else begin
|
||||||
|
errors = errors + 1;
|
||||||
|
$error("Interrupt should be low!");
|
||||||
|
end
|
||||||
|
set_interrupts(0);
|
||||||
|
assert (int_out == 0) else begin
|
||||||
|
errors = errors + 1;
|
||||||
|
$error("Interrupt should be low!");
|
||||||
|
end
|
||||||
|
endtask
|
||||||
|
|
||||||
|
task test_level_irq();
|
||||||
|
$display("Testing level IRQ");
|
||||||
|
do_reset();
|
||||||
|
set_enable(255'hff);
|
||||||
|
set_edge_type(255'hff);
|
||||||
|
set_interrupts(1);
|
||||||
|
assert (int_out == 1) else begin
|
||||||
|
errors = errors + 1;
|
||||||
|
$error("Interrupt should be high!");
|
||||||
|
end
|
||||||
|
send_eoi();
|
||||||
|
assert (int_out == 1) else begin
|
||||||
|
errors = errors + 1;
|
||||||
|
$error("Interrupt should be high!");
|
||||||
|
end
|
||||||
|
set_interrupts(0);
|
||||||
|
send_eoi();
|
||||||
|
assert (int_out == 0) else begin
|
||||||
|
errors = errors + 1;
|
||||||
|
$error("Interrupt should be low!");
|
||||||
|
end
|
||||||
|
endtask
|
||||||
|
|
||||||
|
|
||||||
|
task test_irq_val();
|
||||||
|
int irq_val = -1;
|
||||||
|
$display("Testing IRQ val output");
|
||||||
|
do_reset();
|
||||||
|
set_enable('1);
|
||||||
|
set_edge_type('1);
|
||||||
|
for (int i = 255; i >= 0; i--) begin
|
||||||
|
set_interrupts(BITS_256 << i);
|
||||||
|
read_irqval(irq_val);
|
||||||
|
assert(i == irq_val) else begin
|
||||||
|
errors = errors + 1;
|
||||||
|
$display("Expected %d got %d", i, irq_val);
|
||||||
|
end
|
||||||
|
end
|
||||||
|
|
||||||
|
for (int i = 0; i < 256; i++) begin
|
||||||
|
set_interrupts(BITS_256 >> i);
|
||||||
|
read_irqval(irq_val);
|
||||||
|
assert(int_out == 1) else begin
|
||||||
|
errors = errors + 1;
|
||||||
|
$display("int_out should be asserted!");
|
||||||
|
end
|
||||||
|
assert(0 == irq_val) else begin
|
||||||
|
errors = errors + 1;
|
||||||
|
$display("Expected %d got %d", i, irq_val);
|
||||||
|
end
|
||||||
|
end
|
||||||
|
|
||||||
|
endtask
|
||||||
|
|
||||||
|
int errors;
|
||||||
|
initial begin
|
||||||
|
errors = 0;
|
||||||
|
test_edge_irq();
|
||||||
|
test_level_irq();
|
||||||
|
test_irq_val();
|
||||||
|
if (errors > 0)
|
||||||
|
$finish_and_return(-1);
|
||||||
|
else
|
||||||
|
$finish();
|
||||||
|
end
|
||||||
|
|
||||||
|
initial
|
||||||
|
begin
|
||||||
|
$dumpfile("interrupt_controller_tb.vcd");
|
||||||
|
$dumpvars(0,interrupt_controller_tb);
|
||||||
|
end
|
||||||
|
|
||||||
|
/* These should be shared */
|
||||||
|
task write_reg(input logic [4:0] _addr, input logic [7:0] _data);
|
||||||
|
@(negedge r_clk_cpu);
|
||||||
|
cs <= '1;
|
||||||
|
addr <= _addr;
|
||||||
|
rwb <= '0;
|
||||||
|
i_data <= '1;
|
||||||
|
@(posedge r_clk_cpu);
|
||||||
|
i_data <= _data;
|
||||||
|
@(negedge r_clk_cpu);
|
||||||
|
cs <= '0;
|
||||||
|
rwb <= '1;
|
||||||
|
@(posedge r_clk_cpu);
|
||||||
|
endtask
|
||||||
|
|
||||||
|
task read_reg(input logic [2:0] _addr, output logic [7:0] _data);
|
||||||
|
@(negedge r_clk_cpu);
|
||||||
|
cs <= '1;
|
||||||
|
addr <= _addr;
|
||||||
|
rwb <= '1;
|
||||||
|
i_data <= '1;
|
||||||
|
@(posedge r_clk_cpu);
|
||||||
|
_data <= o_data;
|
||||||
|
@(negedge r_clk_cpu);
|
||||||
|
cs <= '0;
|
||||||
|
rwb <= '1;
|
||||||
|
@(posedge r_clk_cpu);
|
||||||
|
endtask
|
||||||
|
|
||||||
|
task do_reset();
|
||||||
|
repeat (5) @(posedge r_clk_cpu);
|
||||||
|
reset = 1;
|
||||||
|
cs = 0;
|
||||||
|
rwb = 1;
|
||||||
|
addr = '0;
|
||||||
|
i_data = '0;
|
||||||
|
int_in = '0;
|
||||||
|
repeat (5) @(posedge r_clk_cpu);
|
||||||
|
reset = 0;
|
||||||
|
repeat (5) @(posedge r_clk_cpu);
|
||||||
|
endtask
|
||||||
|
|
||||||
|
task set_enable(input logic [255:0] en);
|
||||||
|
for (int i = 0; i < 32; i++) begin
|
||||||
|
write_reg(0, 8'h20 | i);
|
||||||
|
write_reg(1, en[8*i +: 8]);
|
||||||
|
end
|
||||||
|
endtask
|
||||||
|
|
||||||
|
task set_edge_type(input logic [255:0] edge_type);
|
||||||
|
for (int i = 0; i < 32; i++) begin
|
||||||
|
write_reg(0, 8'h40 | i);
|
||||||
|
write_reg(1, edge_type[8*i +: 8]);
|
||||||
|
end
|
||||||
|
endtask
|
||||||
|
|
||||||
|
task set_interrupts(logic [255:0] ints);
|
||||||
|
int_in = ints;
|
||||||
|
@(posedge r_clk_cpu);
|
||||||
|
endtask
|
||||||
|
|
||||||
|
task send_eoi();
|
||||||
|
write_reg(0, 8'hff);
|
||||||
|
write_reg(1, 8'h01);
|
||||||
|
endtask
|
||||||
|
|
||||||
|
task read_irqval(output logic [7:0] _irq_val);
|
||||||
|
write_reg(0, 8'h00);
|
||||||
|
read_reg(1, _irq_val);
|
||||||
|
endtask
|
||||||
|
|
||||||
|
|
||||||
|
endmodule
|
||||||
31
hw/efinix_fpga/src/byte_sel_register.sv
Normal file
31
hw/efinix_fpga/src/byte_sel_register.sv
Normal file
@@ -0,0 +1,31 @@
|
|||||||
|
module byte_sel_register
|
||||||
|
#(
|
||||||
|
parameter DATA_WIDTH = 8,
|
||||||
|
parameter ADDR_WIDTH = 32
|
||||||
|
)(
|
||||||
|
input i_clk,
|
||||||
|
input i_reset,
|
||||||
|
input i_write,
|
||||||
|
input [$clog2(ADDR_WIDTH)-1:0] i_byte_sel,
|
||||||
|
input [DATA_WIDTH-1:0] i_data,
|
||||||
|
output [DATA_WIDTH-1:0] o_data,
|
||||||
|
output [DATA_WIDTH*ADDR_WIDTH-1:0] o_full_data
|
||||||
|
);
|
||||||
|
|
||||||
|
logic [DATA_WIDTH*ADDR_WIDTH-1:0] r_data;
|
||||||
|
|
||||||
|
assign o_data = r_data[DATA_WIDTH*i_byte_sel +: DATA_WIDTH];
|
||||||
|
assign o_full_data = r_data;
|
||||||
|
|
||||||
|
always_ff @(posedge i_clk) begin
|
||||||
|
if (i_reset) begin
|
||||||
|
r_data <= '0;
|
||||||
|
end else begin
|
||||||
|
r_data <= r_data;
|
||||||
|
if (i_write) begin
|
||||||
|
r_data[DATA_WIDTH*i_byte_sel +: DATA_WIDTH] <= i_data;
|
||||||
|
end
|
||||||
|
end
|
||||||
|
end
|
||||||
|
|
||||||
|
endmodule
|
||||||
@@ -4,26 +4,148 @@ module interrupt_controller
|
|||||||
input reset,
|
input reset,
|
||||||
input [7:0] i_data,
|
input [7:0] i_data,
|
||||||
output logic [7:0] o_data,
|
output logic [7:0] o_data,
|
||||||
|
input addr,
|
||||||
input cs,
|
input cs,
|
||||||
input rwb,
|
input rwb,
|
||||||
|
|
||||||
output logic irqb_master,
|
input [255:0] int_in,
|
||||||
|
output logic int_out
|
||||||
input irqb0, irqb1, irqb2, irqb3,
|
|
||||||
input irqb4, irqb5, irqb6, irqb7
|
|
||||||
);
|
);
|
||||||
|
|
||||||
|
logic w_enable_write;
|
||||||
|
logic [7:0] w_enable_data;
|
||||||
|
logic [255:0] w_enable_full_data;
|
||||||
|
|
||||||
//All of the inputs are low level triggered.
|
logic [255:0] int_in_d1;
|
||||||
logic [7:0] irqbv;
|
|
||||||
assign irqbv = {irqb0, irqb1, irqb2, irqb3, irqb4, irqb5, irqb6, irqb7};
|
|
||||||
|
|
||||||
always @(posedge clk) begin
|
logic [4:0] w_byte_sel;
|
||||||
o_data <= irqbv;
|
|
||||||
irqb_master = &irqbv;
|
|
||||||
|
|
||||||
if (cs & ~rwb) begin
|
logic [7:0] irq_val;
|
||||||
o_data <= o_data | i_data;
|
|
||||||
|
byte_sel_register #(
|
||||||
|
.DATA_WIDTH(8),
|
||||||
|
.ADDR_WIDTH(32)
|
||||||
|
) reg_enable (
|
||||||
|
.i_clk(~clk),
|
||||||
|
.i_reset(reset),
|
||||||
|
.i_write(w_enable_write),
|
||||||
|
.i_byte_sel(w_byte_sel),
|
||||||
|
.i_data(i_data),
|
||||||
|
.o_data(w_enable_data),
|
||||||
|
.o_full_data(w_enable_full_data)
|
||||||
|
);
|
||||||
|
|
||||||
|
logic we, re;
|
||||||
|
|
||||||
|
assign we = cs & ~rwb;
|
||||||
|
assign re = cs & rwb;
|
||||||
|
|
||||||
|
logic [255:0] int_masked;
|
||||||
|
assign int_masked = int_in & w_enable_full_data;
|
||||||
|
|
||||||
|
|
||||||
|
logic w_type_write;
|
||||||
|
logic [7:0] w_type_data;
|
||||||
|
logic [255:0] w_type_full_data;
|
||||||
|
|
||||||
|
byte_sel_register #(
|
||||||
|
.DATA_WIDTH(8),
|
||||||
|
.ADDR_WIDTH(32)
|
||||||
|
) reg_type (
|
||||||
|
.i_clk(~clk),
|
||||||
|
.i_reset(reset),
|
||||||
|
.i_write(w_type_write),
|
||||||
|
.i_byte_sel(w_byte_sel),
|
||||||
|
.i_data(i_data),
|
||||||
|
.o_data(w_type_data),
|
||||||
|
.o_full_data(w_type_full_data)
|
||||||
|
);
|
||||||
|
|
||||||
|
logic [7:0] cmd, cmd_next;
|
||||||
|
|
||||||
|
logic w_eoi;
|
||||||
|
|
||||||
|
logic [255:0] r_int, r_int_next;
|
||||||
|
|
||||||
|
always_comb begin
|
||||||
|
w_eoi = 0;
|
||||||
|
|
||||||
|
if (addr == '0 && we) begin
|
||||||
|
cmd_next = i_data;
|
||||||
|
end else begin
|
||||||
|
cmd_next = cmd;
|
||||||
|
end
|
||||||
|
|
||||||
|
|
||||||
|
w_type_write = '0;
|
||||||
|
w_enable_write = '0;
|
||||||
|
|
||||||
|
if (addr == '1) begin
|
||||||
|
unique casez (cmd)
|
||||||
|
8'b000?????: begin
|
||||||
|
o_data = irq_val;
|
||||||
|
end
|
||||||
|
|
||||||
|
8'b001?????: begin
|
||||||
|
w_enable_write = we;
|
||||||
|
w_byte_sel = cmd[4:0];
|
||||||
|
o_data = w_enable_data;
|
||||||
|
end
|
||||||
|
|
||||||
|
8'b010?????: begin
|
||||||
|
w_type_write = we;
|
||||||
|
w_byte_sel = cmd[4:0];
|
||||||
|
o_data = w_type_data;
|
||||||
|
end
|
||||||
|
|
||||||
|
8'hff: begin
|
||||||
|
// Kind of dumb, still requires a data write
|
||||||
|
w_eoi = i_data[0] & we;
|
||||||
|
end
|
||||||
|
endcase
|
||||||
|
end
|
||||||
|
|
||||||
|
int_out = |r_int;
|
||||||
|
|
||||||
|
irq_val = 8'hff;
|
||||||
|
for (int i = 255; i >= 0; i--) begin
|
||||||
|
if (r_int[i] == 1) begin
|
||||||
|
irq_val = i;
|
||||||
|
end
|
||||||
|
end
|
||||||
|
|
||||||
|
for (int i = 0; i < 256; i++) begin
|
||||||
|
case (w_type_full_data[i])
|
||||||
|
0: begin // Edge triggered
|
||||||
|
if (w_eoi && i == irq_val) begin
|
||||||
|
r_int_next[i] = 0;
|
||||||
|
end else begin
|
||||||
|
r_int_next[i] = (~int_in_d1[i] & int_masked[i]) | r_int[i];
|
||||||
|
end
|
||||||
|
end
|
||||||
|
|
||||||
|
1: begin // Level Triggered
|
||||||
|
// If we are trying to clear this interrupt but it is still active,
|
||||||
|
// then we don't actually want to clear it.
|
||||||
|
if (w_eoi && i == irq_val) begin
|
||||||
|
r_int_next[i] = int_masked[i];
|
||||||
|
end else begin
|
||||||
|
r_int_next[i] = r_int[i] | int_masked[i];
|
||||||
|
end
|
||||||
|
end
|
||||||
|
endcase
|
||||||
|
end
|
||||||
|
end
|
||||||
|
|
||||||
|
always_ff @(negedge clk) begin
|
||||||
|
if (reset) begin
|
||||||
|
r_int <= '0;
|
||||||
|
cmd <= '0;
|
||||||
|
int_in_d1 <= '0;
|
||||||
|
end else begin
|
||||||
|
r_int <= r_int_next;
|
||||||
|
cmd <= cmd_next;
|
||||||
|
int_in_d1 <= int_in;
|
||||||
end
|
end
|
||||||
end
|
end
|
||||||
|
|
||||||
|
|||||||
@@ -267,16 +267,7 @@ interrupt_controller u_interrupt_controller(
|
|||||||
.i_data(cpu_data_in),
|
.i_data(cpu_data_in),
|
||||||
.o_data(w_irq_data_out),
|
.o_data(w_irq_data_out),
|
||||||
.cs(w_irq_cs),
|
.cs(w_irq_cs),
|
||||||
.rwb(cpu_rwb),
|
.rwb(cpu_rwb)
|
||||||
.irqb_master(cpu_irqb),
|
|
||||||
.irqb0(w_timer_irqb),
|
|
||||||
.irqb1('1),
|
|
||||||
.irqb2('1),
|
|
||||||
.irqb3('1),
|
|
||||||
.irqb4('1),
|
|
||||||
.irqb5('1),
|
|
||||||
.irqb6('1),
|
|
||||||
.irqb7('1)
|
|
||||||
);
|
);
|
||||||
|
|
||||||
|
|
||||||
|
|||||||
@@ -1,5 +1,5 @@
|
|||||||
<?xml version="1.0" encoding="UTF-8"?>
|
<?xml version="1.0" encoding="UTF-8"?>
|
||||||
<efx:project name="super6502" description="" last_change_date="Thu October 19 2023 18:55:10" location="/home/byron/ServerProjects/super6502/hw/efinix_fpga" sw_version="2022.2.322" last_run_state="fail" last_run_tool="efx_map" last_run_flow="syn" config_result_in_sync="sync" design_ood="" place_ood="sync" route_ood="sync" xmlns:efx="http://www.efinixinc.com/enf_proj" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:schemaLocation="http://www.efinixinc.com/enf_proj enf_proj.xsd">
|
<efx:project name="super6502" description="" last_change_date="Tue October 31 2023 23:42:24" location="/home/byron/Projects/super6502/hw/efinix_fpga" sw_version="2023.1.150" last_run_state="pass" last_run_tool="efx_pgm" last_run_flow="bitstream" config_result_in_sync="sync" design_ood="sync" place_ood="sync" route_ood="sync" xmlns:efx="http://www.efinixinc.com/enf_proj" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:schemaLocation="http://www.efinixinc.com/enf_proj enf_proj.xsd">
|
||||||
<efx:device_info>
|
<efx:device_info>
|
||||||
<efx:family name="Trion"/>
|
<efx:family name="Trion"/>
|
||||||
<efx:device name="T20F256"/>
|
<efx:device name="T20F256"/>
|
||||||
@@ -20,6 +20,7 @@
|
|||||||
<efx:design_file name="src/rom.sv" version="default" library="default"/>
|
<efx:design_file name="src/rom.sv" version="default" library="default"/>
|
||||||
<efx:design_file name="src/spi_controller.sv" version="default" library="default"/>
|
<efx:design_file name="src/spi_controller.sv" version="default" library="default"/>
|
||||||
<efx:design_file name="src/mapper.sv" version="default" library="default"/>
|
<efx:design_file name="src/mapper.sv" version="default" library="default"/>
|
||||||
|
<efx:design_file name="src/byte_sel_register.sv" version="default" library="default"/>
|
||||||
<efx:top_vhdl_arch name=""/>
|
<efx:top_vhdl_arch name=""/>
|
||||||
</efx:design_info>
|
</efx:design_info>
|
||||||
<efx:constraint_info>
|
<efx:constraint_info>
|
||||||
|
|||||||
Reference in New Issue
Block a user