Add sim uart

hw/efinix_fpga/simulation/src/sim_top.sv

@@ -73,17 +73,16 @@ cpu_65c02 u_cpu(
     .WE(w_cpu_we)
 );
 
+logic w_dut_uart_rx, w_dut_uart_tx;
+
+sim_uart u_sim_uart(
+    .clk_50(r_clk_50),
+    .reset(~w_cpu_reset),
+    .rx_i(w_dut_uart_tx),
+    .tx_o(w_dut_uart_rx)
+);
 
-// Having the super6502 causes an infinite loop,
-// but just the rom works. Need to whittle down
-// which block is causing it.
-// rom #(.DATA_WIDTH(8), .ADDR_WIDTH(12)) u_rom(
-//     .addr(w_cpu_addr[11:0]),
-//     .clk(r_clk_2),
-//     .data(w_cpu_data_from_dut)
-// );
 
-//TODO: also this
 super6502 u_dut(
     .i_sysclk(r_sysclk),
     .i_sdrclk(r_sdrclk),
@@ -99,6 +98,9 @@ super6502 u_dut(
     .cpu_rdy(w_cpu_rdy),
     .cpu_phi2(w_cpu_phi2),
 
+    .uart_rx(w_dut_uart_rx),
+    .uart_tx(w_dut_uart_tx),
+
     .o_sdr_CKE(w_sdr_CKE),
     .o_sdr_n_CS(w_sdr_n_CS),
     .o_sdr_n_WE(w_sdr_n_WE),
@@ -150,5 +152,4 @@ generate
     end
 endgenerate
 
-
 endmodule

hw/efinix_fpga/simulation/src/sim_uart/sim_uart.sv

@@ -0,0 +1,43 @@
+module sim_uart(
+    input clk,
+    input clk_50,
+    input reset,
+
+    input [7:0] i_data,
+
+    input rx_i,
+    output tx_o
+);
+
+logic tx_busy, rx_busy;
+
+logic rx_data_valid, rx_error, rx_parity_error;
+logic baud_x16_ce;
+
+logic tx_en;
+
+logic [7:0] tx_data, rx_data;
+
+uart u_uart(
+    .tx_o ( tx_o ),
+    .rx_i ( rx_i ),
+    .tx_busy ( tx_busy ),
+    .rx_data ( rx_data ),
+    .rx_data_valid ( rx_data_valid ),
+    .rx_error ( rx_error ),
+    .rx_parity_error ( rx_parity_error ),
+    .rx_busy ( rx_busy ),
+    .baud_x16_ce ( baud_x16_ce ),
+    .clk ( clk_50 ),
+    .reset ( reset ),
+    .tx_data ( tx_data ),
+    .baud_rate ( baud_rate ),
+    .tx_en ( tx_en )
+);
+
+always @(posedge baud_x16_ce) begin
+    if (rx_data_valid)
+        $display("UART: %c", rx_data);
+end
+
+endmodule