Add board-io, replace sevenseg in sw

hw/fpga/addr_decode.sv

@@ -5,7 +5,8 @@ module addr_decode(
     output logic rom_cs,
     output logic hex_cs,
     output logic uart_cs,
-    output logic irq_cs
+    output logic irq_cs,
+    output logic board_io_cs
 );
 
 assign rom_cs = addr >= 16'h8000;
@@ -13,6 +14,7 @@ assign ram_cs = addr < 16'h4000;
 assign sdram_cs = addr >= 16'h4000 && addr < 16'h7ff0;
 assign hex_cs = addr >= 16'h7ff0 && addr < 16'h7ff4;
 assign uart_cs = addr >= 16'h7ff4 && addr < 16'h7ff6;
+assign board_io_cs = addr == 16'h7ff6;
 assign irq_cs  = addr == 16'h7fff;
 
 endmodule

hw/fpga/board_io.sv

@@ -0,0 +1,27 @@
+module board_io(
+    input clk,
+    input rst,
+    
+    input rw,
+
+    input [7:0] data_in,
+    input cs,
+    input [1:0] addr,
+    
+    output logic [7:0] data_out,
+
+    output logic [7:0] led,
+    input [7:0] sw
+);
+
+assign data_out = sw;
+
+
+always_ff @(posedge clk) begin
+    if (rst)
+        led = '0;
+    if (~rw & cs)
+        led <= data_in;
+end
+
+endmodule

hw/fpga/hvl/cs_testbench.sv

@@ -9,10 +9,11 @@ logic ram_cs;
 logic sdram_cs;
 logic rom_cs;
 logic hex_cs;
+logic board_io_cs;
 logic uart_cs;
 logic irq_cs;
 
-int cs_count = ram_cs + sdram_cs + rom_cs + hex_cs + uart_cs;
+int cs_count = ram_cs + sdram_cs + rom_cs + hex_cs + uart_cs + board_io_cs;
 
 addr_decode dut(.*);
 
@@ -44,6 +45,11 @@ initial begin : TEST_VECTORS
             else
                 $error("Bad CS! addr=%4x should have uart_cs!", addr);
         end
+        if (i == 16'h7ff6) begin
+            assert(board_io_cs == '1)
+            else
+                $error("Bad CS! addr=%4x should have board_io_cs!", addr);
+        end
         if (i == 16'h7fff) begin
             assert(irq_cs == '1)
             else

hw/fpga/super6502.sv

@@ -26,6 +26,9 @@ module super6502(
     input   logic           UART_RXD,
     output  logic           UART_TXD,
 
+    input [7:0] SW,
+    output [7:0] LED,
+
     ///////// SDRAM /////////
     output             DRAM_CLK,
     output             DRAM_CKE,
@@ -57,6 +60,7 @@ logic [7:0] ram_data_out;
 logic [7:0] sdram_data_out;
 logic [7:0] uart_data_out;
 logic [7:0] irq_data_out;
+logic [7:0] board_io_data_out;
 
 logic ram_cs;
 logic sdram_cs;
@@ -64,6 +68,7 @@ logic rom_cs;
 logic hex_cs;
 logic uart_cs;
 logic irq_cs;
+logic board_io_cs;
 
 cpu_clk cpu_clk(
 	.inclk0(clk_50),
@@ -88,7 +93,8 @@ addr_decode decode(
     .rom_cs(rom_cs),
     .hex_cs(hex_cs),
     .uart_cs(uart_cs),
-    .irq_cs(irq_cs)
+    .irq_cs(irq_cs),
+    .board_io_cs(board_io_cs)
 );
 
 
@@ -103,6 +109,8 @@ always_comb begin
         cpu_data_out = uart_data_out;
     else if (irq_cs)
         cpu_data_out = irq_data_out;
+    else if (board_io_cs)
+        cpu_data_out = board_io_data_out;
     else
         cpu_data_out = 'x;
 end
@@ -157,6 +165,17 @@ SevenSeg segs(
     .HEX0(HEX0), .HEX1(HEX1), .HEX2(HEX2), .HEX3(HEX3), .HEX4(HEX4), .HEX5(HEX5)
 );
 
+board_io board_io(
+    .clk(clk),
+    .rst(rst),
+    .rw(cpu_rwb),
+    .data_in(cpu_data_in),
+    .data_out(board_io_data_out),
+    .cs(board_io_cs),
+    .led(LED),
+    .sw(SW)
+);
+
 logic uart_irq;
 
 uart uart(