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Merge branch 'sdram' into 'master'

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Add SDRAM controller (controller)

See merge request bslathi19/super6502!7
This commit is contained in:
Byron Lathi
2022-03-17 22:57:16 +00:00
parent c0d7766bc6 42a718408d
commit 63b942e29a
12 changed files with 608 additions and 31 deletions
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1
.gitlab-ci.yml
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@@ -15,6 +15,7 @@ build-fpga:
image: bslathi19/modelsim_18.1:lite
script:
- cd hw/fpga/
- qsys-generate /builds/bslathi19/super6502/hw/fpga/sdram_platform.qsys --synthesis=VERILOG --output-directory=/builds/bslathi19/super6502/hw/fpga/sdram_platform --family="MAX 10" --part=10M50DAF484C7G
- quartus_map super6502 -c super6502
test_addr_decode:

5
hw/fpga/.gitignore vendored
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@@ -23,8 +23,6 @@
# design.
# Need to keep all HDL files
# *.vhd
# *.v
# Don't keep signal tap files.
*.stp
@@ -52,6 +50,7 @@
*.smsg
*.sof
*.sopc_builder
*.sopcinfo
*.summary
*.tcl
*.txt # Explicitly add any text files used
@@ -71,5 +70,7 @@ greybox_tmp/
incremental_db/
db/
output_files/
.qsys_edit/
sdram_platform/
PLLJ_PLLSPE_INFO.txt

6
hw/fpga/addr_decode.sv
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@@ -1,14 +1,16 @@
module addr_decode(
input logic [15:0] addr,
output logic ram_cs,
output logic sdram_cs,
output logic rom_cs,
output logic hex_cs,
output logic uart_cs,
output logic irq_cs
);
assign rom_cs = addr[15];
assign ram_cs = ~addr[15] && addr < 16'h7ff0;
assign rom_cs = addr >= 16'h8000;
assign ram_cs = addr < 16'h4000;
assign sdram_cs = addr >= 16'h4000 && addr < 16'h7ff0;
assign hex_cs = addr >= 16'h7ff0 && addr < 16'h7ff4;
assign uart_cs = addr >= 16'h7ff4 && addr < 16'h7ff6;
assign irq_cs = addr == 16'h7fff;

10
hw/fpga/hvl/cs_testbench.sv
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@@ -6,12 +6,13 @@ timeprecision 1ns;
logic [15:0] addr;
logic ram_cs;
logic sdram_cs;
logic rom_cs;
logic hex_cs;
logic uart_cs;
logic irq_cs;
int cs_count = ram_cs + rom_cs + hex_cs + uart_cs;
int cs_count = ram_cs + sdram_cs + rom_cs + hex_cs + uart_cs;
addr_decode dut(.*);
@@ -23,11 +24,16 @@ initial begin : TEST_VECTORS
assert(cs_count < 2)
else
$error("Multiple chip selects present!");
if (i < 16'h7ff0) begin
if (i < 16'h4000) begin
assert(ram_cs == '1)
else
$error("Bad CS! addr=%4x should have ram_cs!", addr);
end
if (i >= 16'h4000 && i < 16'h7ff0) begin
assert(sdram_cs == '1)
else
$error("Bad CS! addr=%4x should have sdram_cs!", addr);
end
if (i >= 16'h7ff0 && i < 16'h7ff4) begin
assert(hex_cs == '1)
else

87
hw/fpga/sdram.sv Normal file
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@@ -0,0 +1,87 @@
module sdram(
input rst,
input clk_50,
input cpu_clk,
input [15:0] addr,
input sdram_cs,
input rwb,
input [7:0] data_in,
output [7:0] data_out,
///////// SDRAM /////////
output wire DRAM_CLK,
output wire DRAM_CKE,
output wire [12: 0] DRAM_ADDR,
output wire [ 1: 0] DRAM_BA,
inout wire [15: 0] DRAM_DQ,
output wire DRAM_LDQM,
output wire DRAM_UDQM,
output wire DRAM_CS_N,
output wire DRAM_WE_N,
output wire DRAM_CAS_N,
output wire DRAM_RAS_N
);
enum logic {ACCESS, WAIT } state, next_state;
logic ack;
logic _sdram_cs;
always @(posedge clk_50) begin
if (rst)
state <= ACCESS;
else
state <= next_state;
end
always_comb begin
next_state = state;
case (state)
ACCESS: begin
if (sdram_cs & ~rwb & ack)
next_state = WAIT;
end
WAIT: begin
if (~cpu_clk)
next_state = ACCESS;
end
endcase
end
always_comb begin
_sdram_cs = '0;
case (state)
ACCESS: begin
_sdram_cs = sdram_cs & cpu_clk;
end
WAIT: begin
_sdram_cs = '0;
end
endcase
end
sdram_platform u0 (
.clk_clk (clk_50), // clk.clk
.reset_reset_n (1'b1), // reset.reset_n
.ext_bus_address (addr), // ext_bus.address
.ext_bus_byte_enable (1'b1), // .byte_enable
.ext_bus_read (_sdram_cs & rwb), // .read
.ext_bus_write (_sdram_cs & ~rwb), // .write
.ext_bus_write_data (data_in), // .write_data
.ext_bus_acknowledge (ack), // .acknowledge
.ext_bus_read_data (data_out), // .read_data
//SDRAM
.sdram_clk_clk(DRAM_CLK), //clk_sdram.clk
.sdram_wire_addr(DRAM_ADDR), //sdram_wire.addr
.sdram_wire_ba(DRAM_BA), //.ba
.sdram_wire_cas_n(DRAM_CAS_N), //.cas_n
.sdram_wire_cke(DRAM_CKE), //.cke
.sdram_wire_cs_n(DRAM_CS_N), //.cs_n
.sdram_wire_dq(DRAM_DQ), //.dq
.sdram_wire_dqm({DRAM_UDQM,DRAM_LDQM}), //.dqm
.sdram_wire_ras_n(DRAM_RAS_N), //.ras_n
.sdram_wire_we_n(DRAM_WE_N) //.we_n
);
endmodule

334
hw/fpga/sdram_platform.qsys Normal file
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@@ -0,0 +1,334 @@
<?xml version="1.0" encoding="UTF-8"?>
<system name="$${FILENAME}">
<component
name="$${FILENAME}"
displayName="$${FILENAME}"
version="1.0"
description=""
tags="INTERNAL_COMPONENT=true"
categories="System" />
<parameter name="bonusData"><![CDATA[bonusData
{
element clk_0
{
datum _sortIndex
{
value = "0";
type = "int";
}
}
element ext_bridge
{
datum _sortIndex
{
value = "3";
type = "int";
}
}
element sdram
{
datum _sortIndex
{
value = "1";
type = "int";
}
}
element sdram.s1
{
datum baseAddress
{
value = "0";
type = "String";
}
}
element sdram_pll
{
datum _sortIndex
{
value = "2";
type = "int";
}
}
element sdram_pll.pll_slave
{
datum baseAddress
{
value = "67108864";
type = "String";
}
}
}
]]></parameter>
<parameter name="clockCrossingAdapter" value="HANDSHAKE" />
<parameter name="device" value="10M50DAF484C7G" />
<parameter name="deviceFamily" value="MAX 10" />
<parameter name="deviceSpeedGrade" value="7" />
<parameter name="fabricMode" value="QSYS" />
<parameter name="generateLegacySim" value="false" />
<parameter name="generationId" value="0" />
<parameter name="globalResetBus" value="false" />
<parameter name="hdlLanguage" value="VERILOG" />
<parameter name="hideFromIPCatalog" value="true" />
<parameter name="lockedInterfaceDefinition" value="" />
<parameter name="maxAdditionalLatency" value="1" />
<parameter name="projectName" value="super6502.qpf" />
<parameter name="sopcBorderPoints" value="false" />
<parameter name="systemHash" value="0" />
<parameter name="testBenchDutName" value="" />
<parameter name="timeStamp" value="0" />
<parameter name="useTestBenchNamingPattern" value="false" />
<instanceScript></instanceScript>
<interface name="clk" internal="clk_0.clk_in" type="clock" dir="end" />
<interface
name="ext_bus"
internal="ext_bridge.external_interface"
type="conduit"
dir="end" />
<interface name="reset" internal="clk_0.clk_in_reset" type="reset" dir="end" />
<interface name="sdram_clk" internal="sdram_pll.c1" type="clock" dir="start" />
<interface name="sdram_wire" internal="sdram.wire" type="conduit" dir="end" />
<module name="clk_0" kind="clock_source" version="18.1" enabled="1">
<parameter name="clockFrequency" value="50000000" />
<parameter name="clockFrequencyKnown" value="true" />
<parameter name="inputClockFrequency" value="0" />
<parameter name="resetSynchronousEdges" value="NONE" />
</module>
<module
name="ext_bridge"
kind="altera_up_external_bus_to_avalon_bridge"
version="18.0"
enabled="1">
<parameter name="AUTO_CLK_CLOCK_RATE" value="50000000" />
<parameter name="AUTO_DEVICE_FAMILY" value="MAX 10" />
<parameter name="addr_size" value="64" />
<parameter name="addr_size_multiplier" value="Mbytes" />
<parameter name="data_size" value="8" />
</module>
<module
name="sdram"
kind="altera_avalon_new_sdram_controller"
version="18.1"
enabled="1">
<parameter name="TAC" value="5.4" />
<parameter name="TMRD" value="3" />
<parameter name="TRCD" value="20.0" />
<parameter name="TRFC" value="70.0" />
<parameter name="TRP" value="20.0" />
<parameter name="TWR" value="14.0" />
<parameter name="casLatency" value="3" />
<parameter name="clockRate" value="50000000" />
<parameter name="columnWidth" value="10" />
<parameter name="componentName" value="$${FILENAME}_sdram" />
<parameter name="dataWidth" value="16" />
<parameter name="generateSimulationModel" value="false" />
<parameter name="initNOPDelay" value="0.0" />
<parameter name="initRefreshCommands" value="2" />
<parameter name="masteredTristateBridgeSlave" value="0" />
<parameter name="model">single_Micron_MT48LC4M32B2_7_chip</parameter>
<parameter name="numberOfBanks" value="4" />
<parameter name="numberOfChipSelects" value="1" />
<parameter name="pinsSharedViaTriState" value="false" />
<parameter name="powerUpDelay" value="200.0" />
<parameter name="refreshPeriod" value="15.625" />
<parameter name="registerDataIn" value="true" />
<parameter name="rowWidth" value="13" />
</module>
<module name="sdram_pll" kind="altpll" version="18.1" enabled="1">
<parameter name="AUTO_DEVICE_FAMILY" value="MAX 10" />
<parameter name="AUTO_INCLK_INTERFACE_CLOCK_RATE" value="50000000" />
<parameter name="AVALON_USE_SEPARATE_SYSCLK" value="NO" />
<parameter name="BANDWIDTH" value="" />
<parameter name="BANDWIDTH_TYPE" value="AUTO" />
<parameter name="CLK0_DIVIDE_BY" value="1" />
<parameter name="CLK0_DUTY_CYCLE" value="50" />
<parameter name="CLK0_MULTIPLY_BY" value="1" />
<parameter name="CLK0_PHASE_SHIFT" value="0" />
<parameter name="CLK1_DIVIDE_BY" value="1" />
<parameter name="CLK1_DUTY_CYCLE" value="50" />
<parameter name="CLK1_MULTIPLY_BY" value="1" />
<parameter name="CLK1_PHASE_SHIFT" value="-1000" />
<parameter name="CLK2_DIVIDE_BY" value="" />
<parameter name="CLK2_DUTY_CYCLE" value="" />
<parameter name="CLK2_MULTIPLY_BY" value="" />
<parameter name="CLK2_PHASE_SHIFT" value="" />
<parameter name="CLK3_DIVIDE_BY" value="" />
<parameter name="CLK3_DUTY_CYCLE" value="" />
<parameter name="CLK3_MULTIPLY_BY" value="" />
<parameter name="CLK3_PHASE_SHIFT" value="" />
<parameter name="CLK4_DIVIDE_BY" value="" />
<parameter name="CLK4_DUTY_CYCLE" value="" />
<parameter name="CLK4_MULTIPLY_BY" value="" />
<parameter name="CLK4_PHASE_SHIFT" value="" />
<parameter name="CLK5_DIVIDE_BY" value="" />
<parameter name="CLK5_DUTY_CYCLE" value="" />
<parameter name="CLK5_MULTIPLY_BY" value="" />
<parameter name="CLK5_PHASE_SHIFT" value="" />
<parameter name="CLK6_DIVIDE_BY" value="" />
<parameter name="CLK6_DUTY_CYCLE" value="" />
<parameter name="CLK6_MULTIPLY_BY" value="" />
<parameter name="CLK6_PHASE_SHIFT" value="" />
<parameter name="CLK7_DIVIDE_BY" value="" />
<parameter name="CLK7_DUTY_CYCLE" value="" />
<parameter name="CLK7_MULTIPLY_BY" value="" />
<parameter name="CLK7_PHASE_SHIFT" value="" />
<parameter name="CLK8_DIVIDE_BY" value="" />
<parameter name="CLK8_DUTY_CYCLE" value="" />
<parameter name="CLK8_MULTIPLY_BY" value="" />
<parameter name="CLK8_PHASE_SHIFT" value="" />
<parameter name="CLK9_DIVIDE_BY" value="" />
<parameter name="CLK9_DUTY_CYCLE" value="" />
<parameter name="CLK9_MULTIPLY_BY" value="" />
<parameter name="CLK9_PHASE_SHIFT" value="" />
<parameter name="COMPENSATE_CLOCK" value="CLK0" />
<parameter name="DOWN_SPREAD" value="" />
<parameter name="DPA_DIVIDER" value="" />
<parameter name="DPA_DIVIDE_BY" value="" />
<parameter name="DPA_MULTIPLY_BY" value="" />
<parameter name="ENABLE_SWITCH_OVER_COUNTER" value="" />
<parameter name="EXTCLK0_DIVIDE_BY" value="" />
<parameter name="EXTCLK0_DUTY_CYCLE" value="" />
<parameter name="EXTCLK0_MULTIPLY_BY" value="" />
<parameter name="EXTCLK0_PHASE_SHIFT" value="" />
<parameter name="EXTCLK1_DIVIDE_BY" value="" />
<parameter name="EXTCLK1_DUTY_CYCLE" value="" />
<parameter name="EXTCLK1_MULTIPLY_BY" value="" />
<parameter name="EXTCLK1_PHASE_SHIFT" value="" />
<parameter name="EXTCLK2_DIVIDE_BY" value="" />
<parameter name="EXTCLK2_DUTY_CYCLE" value="" />
<parameter name="EXTCLK2_MULTIPLY_BY" value="" />
<parameter name="EXTCLK2_PHASE_SHIFT" value="" />
<parameter name="EXTCLK3_DIVIDE_BY" value="" />
<parameter name="EXTCLK3_DUTY_CYCLE" value="" />
<parameter name="EXTCLK3_MULTIPLY_BY" value="" />
<parameter name="EXTCLK3_PHASE_SHIFT" value="" />
<parameter name="FEEDBACK_SOURCE" value="" />
<parameter name="GATE_LOCK_COUNTER" value="" />
<parameter name="GATE_LOCK_SIGNAL" value="" />
<parameter name="HIDDEN_CONSTANTS">CT#PORT_clk5 PORT_UNUSED CT#PORT_clk4 PORT_UNUSED CT#PORT_clk3 PORT_UNUSED CT#PORT_clk2 PORT_UNUSED CT#PORT_clk1 PORT_USED CT#PORT_clk0 PORT_USED CT#CLK0_MULTIPLY_BY 1 CT#PORT_SCANWRITE PORT_UNUSED CT#PORT_SCANACLR PORT_UNUSED CT#PORT_PFDENA PORT_UNUSED CT#PORT_PLLENA PORT_UNUSED CT#PORT_SCANDATA PORT_UNUSED CT#PORT_SCANCLKENA PORT_UNUSED CT#WIDTH_CLOCK 5 CT#PORT_SCANDATAOUT PORT_UNUSED CT#LPM_TYPE altpll CT#PLL_TYPE AUTO CT#CLK0_PHASE_SHIFT 0 CT#CLK1_DUTY_CYCLE 50 CT#PORT_PHASEDONE PORT_UNUSED CT#OPERATION_MODE NORMAL CT#PORT_CONFIGUPDATE PORT_UNUSED CT#CLK1_MULTIPLY_BY 1 CT#COMPENSATE_CLOCK CLK0 CT#PORT_CLKSWITCH PORT_UNUSED CT#INCLK0_INPUT_FREQUENCY 20000 CT#PORT_SCANDONE PORT_UNUSED CT#PORT_CLKLOSS PORT_UNUSED CT#PORT_INCLK1 PORT_UNUSED CT#AVALON_USE_SEPARATE_SYSCLK NO CT#PORT_INCLK0 PORT_USED CT#PORT_clkena5 PORT_UNUSED CT#PORT_clkena4 PORT_UNUSED CT#PORT_clkena3 PORT_UNUSED CT#PORT_clkena2 PORT_UNUSED CT#PORT_clkena1 PORT_UNUSED CT#PORT_clkena0 PORT_UNUSED CT#CLK1_PHASE_SHIFT -1000 CT#PORT_ARESET PORT_UNUSED CT#BANDWIDTH_TYPE AUTO CT#INTENDED_DEVICE_FAMILY {MAX 10} CT#PORT_SCANREAD PORT_UNUSED CT#PORT_PHASESTEP PORT_UNUSED CT#PORT_SCANCLK PORT_UNUSED CT#PORT_CLKBAD1 PORT_UNUSED CT#PORT_CLKBAD0 PORT_UNUSED CT#PORT_FBIN PORT_UNUSED CT#PORT_PHASEUPDOWN PORT_UNUSED CT#PORT_extclk3 PORT_UNUSED CT#PORT_extclk2 PORT_UNUSED CT#PORT_extclk1 PORT_UNUSED CT#PORT_PHASECOUNTERSELECT PORT_UNUSED CT#PORT_extclk0 PORT_UNUSED CT#PORT_ACTIVECLOCK PORT_UNUSED CT#CLK0_DUTY_CYCLE 50 CT#CLK0_DIVIDE_BY 1 CT#CLK1_DIVIDE_BY 1 CT#PORT_LOCKED PORT_UNUSED</parameter>
<parameter name="HIDDEN_CUSTOM_ELABORATION">altpll_avalon_elaboration</parameter>
<parameter name="HIDDEN_CUSTOM_POST_EDIT">altpll_avalon_post_edit</parameter>
<parameter name="HIDDEN_IF_PORTS">IF#phasecounterselect {input 3} IF#locked {output 0} IF#reset {input 0} IF#clk {input 0} IF#phaseupdown {input 0} IF#scandone {output 0} IF#readdata {output 32} IF#write {input 0} IF#scanclk {input 0} IF#phasedone {output 0} IF#c4 {output 0} IF#c3 {output 0} IF#c2 {output 0} IF#address {input 2} IF#c1 {output 0} IF#c0 {output 0} IF#writedata {input 32} IF#read {input 0} IF#areset {input 0} IF#scanclkena {input 0} IF#scandataout {output 0} IF#configupdate {input 0} IF#phasestep {input 0} IF#scandata {input 0}</parameter>
<parameter name="HIDDEN_IS_FIRST_EDIT" value="0" />
<parameter name="HIDDEN_IS_NUMERIC">IN#WIDTH_CLOCK 1 IN#CLK0_DUTY_CYCLE 1 IN#PLL_TARGET_HARCOPY_CHECK 1 IN#CLK1_MULTIPLY_BY 1 IN#SWITCHOVER_COUNT_EDIT 1 IN#INCLK0_INPUT_FREQUENCY 1 IN#PLL_LVDS_PLL_CHECK 1 IN#PLL_AUTOPLL_CHECK 1 IN#PLL_FASTPLL_CHECK 1 IN#CLK1_DUTY_CYCLE 1 IN#PLL_ENHPLL_CHECK 1 IN#DIV_FACTOR1 1 IN#DIV_FACTOR0 1 IN#LVDS_MODE_DATA_RATE_DIRTY 1 IN#GLOCK_COUNTER_EDIT 1 IN#CLK0_DIVIDE_BY 1 IN#MULT_FACTOR1 1 IN#MULT_FACTOR0 1 IN#CLK0_MULTIPLY_BY 1 IN#USE_MIL_SPEED_GRADE 1 IN#CLK1_DIVIDE_BY 1</parameter>
<parameter name="HIDDEN_MF_PORTS">MF#areset 1 MF#clk 1 MF#locked 1 MF#inclk 1</parameter>
<parameter name="HIDDEN_PRIVATES">PT#GLOCKED_FEATURE_ENABLED 0 PT#SPREAD_FEATURE_ENABLED 0 PT#BANDWIDTH_FREQ_UNIT MHz PT#CUR_DEDICATED_CLK c0 PT#INCLK0_FREQ_EDIT 50.000 PT#BANDWIDTH_PRESET Low PT#PLL_LVDS_PLL_CHECK 0 PT#BANDWIDTH_USE_PRESET 0 PT#AVALON_USE_SEPARATE_SYSCLK NO PT#PLL_ENHPLL_CHECK 0 PT#OUTPUT_FREQ_UNIT1 MHz PT#OUTPUT_FREQ_UNIT0 MHz PT#PHASE_RECONFIG_FEATURE_ENABLED 1 PT#CREATE_CLKBAD_CHECK 0 PT#CLKSWITCH_CHECK 0 PT#INCLK1_FREQ_EDIT 100.000 PT#NORMAL_MODE_RADIO 1 PT#SRC_SYNCH_COMP_RADIO 0 PT#PLL_ARESET_CHECK 0 PT#LONG_SCAN_RADIO 1 PT#SCAN_FEATURE_ENABLED 1 PT#PHASE_RECONFIG_INPUTS_CHECK 0 PT#USE_CLK1 1 PT#USE_CLK0 1 PT#PRIMARY_CLK_COMBO inclk0 PT#BANDWIDTH 1.000 PT#GLOCKED_COUNTER_EDIT_CHANGED 1 PT#PLL_FASTPLL_CHECK 0 PT#SPREAD_FREQ_UNIT KHz PT#PLL_AUTOPLL_CHECK 1 PT#LVDS_PHASE_SHIFT_UNIT1 deg PT#LVDS_PHASE_SHIFT_UNIT0 deg PT#OUTPUT_FREQ_MODE1 0 PT#SWITCHOVER_FEATURE_ENABLED 0 PT#MIG_DEVICE_SPEED_GRADE Any PT#OUTPUT_FREQ_MODE0 1 PT#BANDWIDTH_FEATURE_ENABLED 1 PT#INCLK0_FREQ_UNIT_COMBO MHz PT#ZERO_DELAY_RADIO 0 PT#OUTPUT_FREQ1 100.00000000 PT#OUTPUT_FREQ0 50.00000000 PT#SHORT_SCAN_RADIO 0 PT#LVDS_MODE_DATA_RATE_DIRTY 0 PT#CUR_FBIN_CLK c0 PT#PLL_ADVANCED_PARAM_CHECK 0 PT#CLKBAD_SWITCHOVER_CHECK 0 PT#PHASE_SHIFT_STEP_ENABLED_CHECK 0 PT#DEVICE_SPEED_GRADE 7 PT#PLL_FBMIMIC_CHECK 0 PT#LVDS_MODE_DATA_RATE {Not Available} PT#LOCKED_OUTPUT_CHECK 0 PT#SPREAD_PERCENT 0.500 PT#PHASE_SHIFT1 -1.00000000 PT#PHASE_SHIFT0 0.00000000 PT#DIV_FACTOR1 1 PT#DIV_FACTOR0 1 PT#CNX_NO_COMPENSATE_RADIO 0 PT#USE_CLKENA1 0 PT#USE_CLKENA0 0 PT#CREATE_INCLK1_CHECK 0 PT#GLOCK_COUNTER_EDIT 1048575 PT#INCLK1_FREQ_UNIT_COMBO MHz PT#EFF_OUTPUT_FREQ_VALUE1 50.000000 PT#EFF_OUTPUT_FREQ_VALUE0 50.000000 PT#SPREAD_FREQ 50.000 PT#USE_MIL_SPEED_GRADE 0 PT#EXPLICIT_SWITCHOVER_COUNTER 0 PT#STICKY_CLK4 0 PT#STICKY_CLK3 0 PT#STICKY_CLK2 0 PT#STICKY_CLK1 1 PT#STICKY_CLK0 1 PT#EXT_FEEDBACK_RADIO 0 PT#MIRROR_CLK1 0 PT#MIRROR_CLK0 0 PT#SWITCHOVER_COUNT_EDIT 1 PT#SELF_RESET_LOCK_LOSS 0 PT#PLL_PFDENA_CHECK 0 PT#INT_FEEDBACK__MODE_RADIO 1 PT#INCLK1_FREQ_EDIT_CHANGED 1 PT#CLKLOSS_CHECK 0 PT#SYNTH_WRAPPER_GEN_POSTFIX 0 PT#PHASE_SHIFT_UNIT1 ns PT#PHASE_SHIFT_UNIT0 deg PT#BANDWIDTH_USE_AUTO 1 PT#HAS_MANUAL_SWITCHOVER 1 PT#MULT_FACTOR1 1 PT#MULT_FACTOR0 1 PT#SPREAD_USE 0 PT#GLOCKED_MODE_CHECK 0 PT#SACN_INPUTS_CHECK 0 PT#DUTY_CYCLE1 50.00000000 PT#INTENDED_DEVICE_FAMILY {MAX 10} PT#DUTY_CYCLE0 50.00000000 PT#PLL_TARGET_HARCOPY_CHECK 0 PT#INCLK1_FREQ_UNIT_CHANGED 1 PT#RECONFIG_FILE ALTPLL1647404711238322.mif PT#ACTIVECLK_CHECK 0</parameter>
<parameter name="HIDDEN_USED_PORTS">UP#locked used UP#c1 used UP#c0 used UP#areset used UP#inclk0 used</parameter>
<parameter name="INCLK0_INPUT_FREQUENCY" value="20000" />
<parameter name="INCLK1_INPUT_FREQUENCY" value="" />
<parameter name="INTENDED_DEVICE_FAMILY" value="MAX 10" />
<parameter name="INVALID_LOCK_MULTIPLIER" value="" />
<parameter name="LOCK_HIGH" value="" />
<parameter name="LOCK_LOW" value="" />
<parameter name="OPERATION_MODE" value="NORMAL" />
<parameter name="PLL_TYPE" value="AUTO" />
<parameter name="PORT_ACTIVECLOCK" value="PORT_UNUSED" />
<parameter name="PORT_ARESET" value="PORT_UNUSED" />
<parameter name="PORT_CLKBAD0" value="PORT_UNUSED" />
<parameter name="PORT_CLKBAD1" value="PORT_UNUSED" />
<parameter name="PORT_CLKLOSS" value="PORT_UNUSED" />
<parameter name="PORT_CLKSWITCH" value="PORT_UNUSED" />
<parameter name="PORT_CONFIGUPDATE" value="PORT_UNUSED" />
<parameter name="PORT_ENABLE0" value="" />
<parameter name="PORT_ENABLE1" value="" />
<parameter name="PORT_FBIN" value="PORT_UNUSED" />
<parameter name="PORT_FBOUT" value="" />
<parameter name="PORT_INCLK0" value="PORT_USED" />
<parameter name="PORT_INCLK1" value="PORT_UNUSED" />
<parameter name="PORT_LOCKED" value="PORT_UNUSED" />
<parameter name="PORT_PFDENA" value="PORT_UNUSED" />
<parameter name="PORT_PHASECOUNTERSELECT" value="PORT_UNUSED" />
<parameter name="PORT_PHASEDONE" value="PORT_UNUSED" />
<parameter name="PORT_PHASESTEP" value="PORT_UNUSED" />
<parameter name="PORT_PHASEUPDOWN" value="PORT_UNUSED" />
<parameter name="PORT_PLLENA" value="PORT_UNUSED" />
<parameter name="PORT_SCANACLR" value="PORT_UNUSED" />
<parameter name="PORT_SCANCLK" value="PORT_UNUSED" />
<parameter name="PORT_SCANCLKENA" value="PORT_UNUSED" />
<parameter name="PORT_SCANDATA" value="PORT_UNUSED" />
<parameter name="PORT_SCANDATAOUT" value="PORT_UNUSED" />
<parameter name="PORT_SCANDONE" value="PORT_UNUSED" />
<parameter name="PORT_SCANREAD" value="PORT_UNUSED" />
<parameter name="PORT_SCANWRITE" value="PORT_UNUSED" />
<parameter name="PORT_SCLKOUT0" value="" />
<parameter name="PORT_SCLKOUT1" value="" />
<parameter name="PORT_VCOOVERRANGE" value="" />
<parameter name="PORT_VCOUNDERRANGE" value="" />
<parameter name="PORT_clk0" value="PORT_USED" />
<parameter name="PORT_clk1" value="PORT_USED" />
<parameter name="PORT_clk2" value="PORT_UNUSED" />
<parameter name="PORT_clk3" value="PORT_UNUSED" />
<parameter name="PORT_clk4" value="PORT_UNUSED" />
<parameter name="PORT_clk5" value="PORT_UNUSED" />
<parameter name="PORT_clk6" value="" />
<parameter name="PORT_clk7" value="" />
<parameter name="PORT_clk8" value="" />
<parameter name="PORT_clk9" value="" />
<parameter name="PORT_clkena0" value="PORT_UNUSED" />
<parameter name="PORT_clkena1" value="PORT_UNUSED" />
<parameter name="PORT_clkena2" value="PORT_UNUSED" />
<parameter name="PORT_clkena3" value="PORT_UNUSED" />
<parameter name="PORT_clkena4" value="PORT_UNUSED" />
<parameter name="PORT_clkena5" value="PORT_UNUSED" />
<parameter name="PORT_extclk0" value="PORT_UNUSED" />
<parameter name="PORT_extclk1" value="PORT_UNUSED" />
<parameter name="PORT_extclk2" value="PORT_UNUSED" />
<parameter name="PORT_extclk3" value="PORT_UNUSED" />
<parameter name="PORT_extclkena0" value="" />
<parameter name="PORT_extclkena1" value="" />
<parameter name="PORT_extclkena2" value="" />
<parameter name="PORT_extclkena3" value="" />
<parameter name="PRIMARY_CLOCK" value="" />
<parameter name="QUALIFY_CONF_DONE" value="" />
<parameter name="SCAN_CHAIN" value="" />
<parameter name="SCAN_CHAIN_MIF_FILE" value="" />
<parameter name="SCLKOUT0_PHASE_SHIFT" value="" />
<parameter name="SCLKOUT1_PHASE_SHIFT" value="" />
<parameter name="SELF_RESET_ON_GATED_LOSS_LOCK" value="" />
<parameter name="SELF_RESET_ON_LOSS_LOCK" value="" />
<parameter name="SKIP_VCO" value="" />
<parameter name="SPREAD_FREQUENCY" value="" />
<parameter name="SWITCH_OVER_COUNTER" value="" />
<parameter name="SWITCH_OVER_ON_GATED_LOCK" value="" />
<parameter name="SWITCH_OVER_ON_LOSSCLK" value="" />
<parameter name="SWITCH_OVER_TYPE" value="" />
<parameter name="USING_FBMIMICBIDIR_PORT" value="" />
<parameter name="VALID_LOCK_MULTIPLIER" value="" />
<parameter name="VCO_DIVIDE_BY" value="" />
<parameter name="VCO_FREQUENCY_CONTROL" value="" />
<parameter name="VCO_MULTIPLY_BY" value="" />
<parameter name="VCO_PHASE_SHIFT_STEP" value="" />
<parameter name="WIDTH_CLOCK" value="5" />
<parameter name="WIDTH_PHASECOUNTERSELECT" value="" />
</module>
<connection
kind="avalon"
version="18.1"
start="ext_bridge.avalon_master"
end="sdram.s1">
<parameter name="arbitrationPriority" value="1" />
<parameter name="baseAddress" value="0x0000" />
<parameter name="defaultConnection" value="false" />
</connection>
<connection kind="clock" version="18.1" start="sdram_pll.c0" end="sdram.clk" />
<connection kind="clock" version="18.1" start="clk_0.clk" end="ext_bridge.clk" />
<connection
kind="clock"
version="18.1"
start="clk_0.clk"
end="sdram_pll.inclk_interface" />
<connection
kind="reset"
version="18.1"
start="clk_0.clk_reset"
end="sdram_pll.inclk_interface_reset" />
<connection kind="reset" version="18.1" start="clk_0.clk_reset" end="sdram.reset" />
<connection
kind="reset"
version="18.1"
start="clk_0.clk_reset"
end="ext_bridge.reset" />
<interconnectRequirement for="$system" name="qsys_mm.clockCrossingAdapter" value="HANDSHAKE" />
<interconnectRequirement for="$system" name="qsys_mm.enableEccProtection" value="FALSE" />
<interconnectRequirement for="$system" name="qsys_mm.insertDefaultSlave" value="FALSE" />
<interconnectRequirement for="$system" name="qsys_mm.maxAdditionalLatency" value="1" />
</system>

105
hw/fpga/super6502.qsf
View File

@@ -188,7 +188,7 @@ set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to cpu_sob
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to cpu_sync
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to clk_50
set_global_assignment -name ENABLE_SIGNALTAP OFF
set_global_assignment -name USE_SIGNALTAP_FILE output_files/stp1.stp
set_global_assignment -name USE_SIGNALTAP_FILE output_files/stp2.stp
set_location_assignment PIN_F20 -to HEX4[6]
set_location_assignment PIN_F19 -to HEX4[5]
set_location_assignment PIN_H19 -to HEX4[4]
@@ -205,17 +205,6 @@ set_location_assignment PIN_F18 -to HEX4[0]
set_location_assignment PIN_E20 -to HEX4[1]
set_location_assignment PIN_AB5 -to UART_RXD
set_location_assignment PIN_AB6 -to UART_TXD
set_global_assignment -name SYSTEMVERILOG_FILE uart.sv
set_global_assignment -name SYSTEMVERILOG_FILE addr_decode.sv
set_global_assignment -name SYSTEMVERILOG_FILE bb_spi_controller.sv
set_global_assignment -name SYSTEMVERILOG_FILE super6502.sv
set_global_assignment -name QIP_FILE ram.qip
set_global_assignment -name SDC_FILE super6502.sdc
set_global_assignment -name QIP_FILE rom.qip
set_global_assignment -name SYSTEMVERILOG_FILE HexDriver.sv
set_global_assignment -name SYSTEMVERILOG_FILE SevenSeg.sv
set_global_assignment -name QIP_FILE cpu_clk.qip
set_global_assignment -name SIGNALTAP_FILE output_files/stp1.stp
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to UART_RXD
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to UART_TXD
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[6]
@@ -283,4 +272,96 @@ set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[8]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[9]
set_location_assignment PIN_A7 -to button_1
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to button_1
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[0]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[10]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[11]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[12]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[1]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[2]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[3]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[4]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[5]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[6]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[7]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[8]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[9]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_BA[0]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_BA[1]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_CAS_N
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_CKE
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_CLK
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_CS_N
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[0]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[10]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[11]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[12]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[13]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[14]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[15]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[1]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[2]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[3]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[4]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[5]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[6]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[7]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[8]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[9]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_LDQM
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_RAS_N
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_UDQM
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_WE_N
set_location_assignment PIN_U17 -to DRAM_ADDR[0]
set_location_assignment PIN_T20 -to DRAM_ADDR[10]
set_location_assignment PIN_P20 -to DRAM_ADDR[11]
set_location_assignment PIN_R20 -to DRAM_ADDR[12]
set_location_assignment PIN_W19 -to DRAM_ADDR[1]
set_location_assignment PIN_V18 -to DRAM_ADDR[2]
set_location_assignment PIN_U18 -to DRAM_ADDR[3]
set_location_assignment PIN_U19 -to DRAM_ADDR[4]
set_location_assignment PIN_T18 -to DRAM_ADDR[5]
set_location_assignment PIN_T19 -to DRAM_ADDR[6]
set_location_assignment PIN_R18 -to DRAM_ADDR[7]
set_location_assignment PIN_P18 -to DRAM_ADDR[8]
set_location_assignment PIN_P19 -to DRAM_ADDR[9]
set_location_assignment PIN_T21 -to DRAM_BA[0]
set_location_assignment PIN_T22 -to DRAM_BA[1]
set_location_assignment PIN_U21 -to DRAM_CAS_N
set_location_assignment PIN_N22 -to DRAM_CKE
set_location_assignment PIN_L14 -to DRAM_CLK
set_location_assignment PIN_U20 -to DRAM_CS_N
set_location_assignment PIN_Y21 -to DRAM_DQ[0]
set_location_assignment PIN_H21 -to DRAM_DQ[10]
set_location_assignment PIN_H22 -to DRAM_DQ[11]
set_location_assignment PIN_G22 -to DRAM_DQ[12]
set_location_assignment PIN_G20 -to DRAM_DQ[13]
set_location_assignment PIN_G19 -to DRAM_DQ[14]
set_location_assignment PIN_F22 -to DRAM_DQ[15]
set_location_assignment PIN_Y20 -to DRAM_DQ[1]
set_location_assignment PIN_AA22 -to DRAM_DQ[2]
set_location_assignment PIN_AA21 -to DRAM_DQ[3]
set_location_assignment PIN_Y22 -to DRAM_DQ[4]
set_location_assignment PIN_W22 -to DRAM_DQ[5]
set_location_assignment PIN_W20 -to DRAM_DQ[6]
set_location_assignment PIN_V21 -to DRAM_DQ[7]
set_location_assignment PIN_P21 -to DRAM_DQ[8]
set_location_assignment PIN_J22 -to DRAM_DQ[9]
set_location_assignment PIN_V22 -to DRAM_LDQM
set_location_assignment PIN_U22 -to DRAM_RAS_N
set_location_assignment PIN_J21 -to DRAM_UDQM
set_location_assignment PIN_V20 -to DRAM_WE_N
set_global_assignment -name SYSTEMVERILOG_FILE sdram.sv
set_global_assignment -name QIP_FILE sdram_platform/synthesis/sdram_platform.qip
set_global_assignment -name SYSTEMVERILOG_FILE uart.sv
set_global_assignment -name SYSTEMVERILOG_FILE addr_decode.sv
set_global_assignment -name SYSTEMVERILOG_FILE bb_spi_controller.sv
set_global_assignment -name SYSTEMVERILOG_FILE super6502.sv
set_global_assignment -name QIP_FILE ram.qip
set_global_assignment -name SDC_FILE super6502.sdc
set_global_assignment -name QIP_FILE rom.qip
set_global_assignment -name SYSTEMVERILOG_FILE HexDriver.sv
set_global_assignment -name SYSTEMVERILOG_FILE SevenSeg.sv
set_global_assignment -name QIP_FILE cpu_clk.qip
set_global_assignment -name SIGNALTAP_FILE output_files/stp1.stp
set_global_assignment -name SIGNALTAP_FILE output_files/stp2.stp
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top

27
hw/fpga/super6502.sdc
View File

@@ -1,11 +1,30 @@
#**************************************************************
# Create Clock (where ‘clk’ is the user-defined system clock name)
#**************************************************************
create_clock -name {clk_50} -period 20ns -waveform {0.000 5.000} [get_ports {clk}]
create_clock -name {clk_50} -period 20ns -waveform {0.000 5.000} [get_ports {clk_50}]
create_generated_clock -source [get_pins {sdram|u0|sdram_pll|sd1|pll7|clk[1] }] \
-name clk_dram_ext [get_ports {DRAM_CLK}]
derive_pll_clocks
# Constrain the input I/O path
set_input_delay -clock {clk} -max 3 [all_inputs]
set_input_delay -clock {clk} -min 2 [all_inputs]
# set_input_delay -clock {clk} -max 3 [all_inputs]
# set_input_delay -clock {clk} -min 2 [all_inputs]
# Constrain the output I/O path
set_output_delay -clock {clk} 2 [all_outputs]
#set_output_delay -clock {clk} 2 [all_outputs]
derive_clock_uncertainty
set_input_delay -max -clock clk_dram_ext 5.9 [get_ports DRAM_DQ*]
set_input_delay -min -clock clk_dram_ext 3.0 [get_ports DRAM_DQ*]
set_multicycle_path -from [get_clocks {clk_dram_ext}] \
-to [get_clocks {sdram|u0|sdram_pll|sd1|pll7|clk[0] }] \
-setup 2
set_output_delay -max -clock clk_dram_ext 1.6 [get_ports {DRAM_DQ* DRAM_*DQM}]
set_output_delay -min -clock clk_dram_ext -0.9 [get_ports {DRAM_DQ* DRAM_*DQM}]
set_output_delay -max -clock clk_dram_ext 1.6 [get_ports {DRAM_ADDR* DRAM_BA* DRAM_RAS_N DRAM_CAS_N DRAM_WE_N DRAM_CKE DRAM_CS_N}]
set_output_delay -min -clock clk_dram_ext -0.9 [get_ports {DRAM_ADDR* DRAM_BA* DRAM_RAS_N DRAM_CAS_N DRAM_WE_N DRAM_CKE DRAM_CS_N}]

42
hw/fpga/super6502.sv
View File

@@ -24,7 +24,20 @@ module super6502(
output logic [6:0] HEX0, HEX1, HEX2, HEX3, HEX4, HEX5,
input logic UART_RXD,
output logic UART_TXD
output logic UART_TXD,
///////// SDRAM /////////
output DRAM_CLK,
output DRAM_CKE,
output [12: 0] DRAM_ADDR,
output [ 1: 0] DRAM_BA,
inout [15: 0] DRAM_DQ,
output DRAM_LDQM,
output DRAM_UDQM,
output DRAM_CS_N,
output DRAM_WE_N,
output DRAM_CAS_N,
output DRAM_RAS_N
);
logic rst;
@@ -41,10 +54,12 @@ assign cpu_data = cpu_rwb ? cpu_data_out : 'z;
logic [7:0] rom_data_out;
logic [7:0] ram_data_out;
logic [7:0] sdram_data_out;
logic [7:0] uart_data_out;
logic [7:0] irq_data_out;
logic ram_cs;
logic sdram_cs;
logic rom_cs;
logic hex_cs;
logic uart_cs;
@@ -69,6 +84,7 @@ assign cpu_irqb = irq_data_out == 0;
addr_decode decode(
.addr(cpu_addr),
.ram_cs(ram_cs),
.sdram_cs(sdram_cs),
.rom_cs(rom_cs),
.hex_cs(hex_cs),
.uart_cs(uart_cs),
@@ -79,6 +95,8 @@ addr_decode decode(
always_comb begin
if (ram_cs)
cpu_data_out = ram_data_out;
else if (sdram_cs)
cpu_data_out = sdram_data_out;
else if (rom_cs)
cpu_data_out = rom_data_out;
else if (uart_cs)
@@ -90,7 +108,29 @@ always_comb begin
end
sdram sdram(
.rst(rst),
.clk_50(clk_50),
.cpu_clk(cpu_phi2),
.addr(cpu_addr),
.sdram_cs(sdram_cs),
.rwb(cpu_rwb),
.data_in(cpu_data_in),
.data_out(sdram_data_out),
//SDRAM
.DRAM_CLK(DRAM_CLK), //clk_sdram.clk
.DRAM_ADDR(DRAM_ADDR), //sdram_wire.addr
.DRAM_BA(DRAM_BA), //.ba
.DRAM_CAS_N(DRAM_CAS_N), //.cas_n
.DRAM_CKE(DRAM_CKE), //.cke
.DRAM_CS_N(DRAM_CS_N), //.cs_n
.DRAM_DQ(DRAM_DQ), //.dq
.DRAM_UDQM(DRAM_UDQM), //.dqm
.DRAM_LDQM(DRAM_LDQM),
.DRAM_RAS_N(DRAM_RAS_N), //.ras_n
.DRAM_WE_N(DRAM_WE_N) //.we_n
);
ram main_memory(
.address(cpu_addr[14:0]),

6
sw/boot.s
View File

@@ -8,7 +8,7 @@
.import _main
.export __STARTUP__ : absolute = 1 ; Mark as startup
.import __RAM_START__, __RAM_SIZE__ ; Linker generated
.import __SDRAM_START__, __SDRAM_SIZE__ ; Linker generated
.import copydata, zerobss, initlib, donelib
@@ -29,9 +29,9 @@ _init: LDX #$FF ; Initialize stack pointer to $01FF
; ---------------------------------------------------------------------------
; Set cc65 argument stack pointer
LDA #<(__RAM_START__ + __RAM_SIZE__)
LDA #<(__SDRAM_START__ + __SDRAM_SIZE__)
STA sp
LDA #>(__RAM_START__ + __RAM_SIZE__)
LDA #>(__SDRAM_START__ + __SDRAM_SIZE__)
STA sp+1
; ---------------------------------------------------------------------------

9
sw/link.ld
View File

@@ -1,15 +1,16 @@
MEMORY
{
ZP: start = $0, size = $100, type = rw, define = yes;
RAM: start = $0200, size = $7D00, type = rw, define = yes;
RAM: start = $0200, size = $3D00, type = rw, define = yes;
SDRAM: start = $4000, size = $3ff0, type = rw, define = yes;
ROM: start = $8000, size = $8000, fill = yes, fillval = $ff, file = %O;
}
SEGMENTS {
ZEROPAGE: load = ZP, type = zp, define = yes;
DATA: load = ROM, type = rw, define = yes, run = RAM;
BSS: load = RAM, type = bss, define = yes;
HEAP: load = RAM, type = bss, optional = yes;
DATA: load = ROM, type = rw, define = yes, run = SDRAM;
BSS: load = SDRAM, type = bss, define = yes;
HEAP: load = SDRAM, type = bss, optional = yes;
STARTUP: load = ROM, type = ro;
ONCE: load = ROM, type = ro, optional = yes;
CODE: load = ROM, type = ro;

7
sw/main.c
View File

@@ -5,16 +5,21 @@
#include "uart.h"
int main() {
int i;
char s[16];
s[15] = 0;
clrscr();
cprintf("Hello, world!\n");
while (1) {
cscanf("%15s", s);
cprintf("\n");
for (i = 0; i < 16; i++)
cprintf("s[%d]=%c ", i, s[i]);
cprintf("\n");
cprintf("Read string: %s\n", s);
}
return 0;
}