Get something simulated

Infinite loop being caused somewhere

hw/efinix_fpga/simulation/Makefile

@@ -8,10 +8,15 @@ INC=$(shell find include/ -type f)
 
 TOP_MODULE=sim_top
 TARGET=sim_top
+INIT_MEM=init_hex.mem
 
-all: 
+all: $(INIT_MEM)
 	iverilog -g2005-sv -s $(TOP_MODULE) -o $(TARGET) $(INC) $(SRCS)
 
+$(INIT_MEM):
+	cp ../$(INIT_MEM) .
+
 .PHONY: clean
 clean:
-	rm -rf $(TARGET)
+	rm -rf $(TARGET)
+	rm $(INIT_MEM)