Add divider

Adds a 16x16 divider to go with the multiplier.

The divider is a single stage with no pipelining, which works at the
slow 2MHz frequency. Doing this lowers the maximum clock frequency to 5.

This is acceptable for now but means that the cpu can't be run at 14,
which is the maximum frequency.

hw/efinix_fpga/test_programs/Makefile

@@ -1,4 +1,4 @@
-TARGETS=stacktest runram timer timer_irq multiplier
+TARGETS=stacktest runram timer timer_irq multiplier divider
 SRC=$(wildcard *.s)
 DIR=../ip/bram
 

hw/efinix_fpga/test_programs/divider.s

@@ -0,0 +1,33 @@
+.code
+
+LEDS = $efff
+
+DIVNL = $efe8
+DIVNH = $efe9
+DIVDL = $efea
+DIVDH = $efeb
+
+DIVQL = $efec
+DIVQH = $efed
+DIVRL = $efee
+DIVRH = $efef
+
+main:
+    lda #$c8
+    sta DIVNL
+    lda #$01
+    sta DIVNH
+    lda #$0d
+    sta DIVDL
+    lda #$00
+    sta DIVDH
+    lda DIVQL
+    sta LEDS
+    wai
+    bra main
+
+.segment "VECTORS"
+
+.addr main
+.addr main
+.addr main