Add basic mapping
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@@ -6,7 +6,7 @@ module mapper(
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output logic [24:0] sdram_addr,
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input cs,
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input rw,
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input rwb,
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input [7:0] i_data,
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output logic [7:0] o_data
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@@ -23,12 +23,29 @@ logic en;
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always_comb begin
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if (!en) begin
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sdram_addr = {9'b0, cpu_addr};
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end else begin
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sdram_addr = {map[cpu_addr[15:12]], cpu_addr[11:0]};
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end
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end
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always_ff @(posedge clk) begin
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if (rst) begin
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en <= '0;
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for (bit [13:0] a = 14'b0; a < 14'h10; a++) begin
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map[a] = a;
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end
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end else begin
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if (~rwb & cs) begin
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if (base_addr == 16'h32) begin
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en <= i_data[0];
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end else begin
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if (!base_addr[0]) begin
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map[base_addr[3:1]] <= {i_data[5:0], map[base_addr[3:1]][7:0]};
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end else begin
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map[base_addr[3:1]] <= {map[base_addr[3:1]][12:8], i_data};
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end
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end
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end
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end
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end
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@@ -216,7 +216,7 @@ mapper u_mapper(
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.cpu_addr(cpu_addr),
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.sdram_addr(w_sdram_addr),
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.cs(w_mapper_cs),
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.rw(cpu_rwb),
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.rwb(cpu_rwb),
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.i_data(cpu_data_in),
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.o_data(w_mapper_data_out)
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);
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@@ -1,5 +1,5 @@
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<?xml version="1.0" encoding="UTF-8"?>
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<efx:project name="super6502" description="" last_change_date="Wed September 6 2023 19:46:49" location="/home/byron/Projects/super6502/hw/efinix_fpga" sw_version="2023.1.150" last_run_state="pass" last_run_tool="efx_pgm" last_run_flow="bitstream" config_result_in_sync="true" design_ood="sync" place_ood="sync" route_ood="sync" xmlns:efx="http://www.efinixinc.com/enf_proj" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:schemaLocation="http://www.efinixinc.com/enf_proj enf_proj.xsd">
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<efx:project name="super6502" description="" last_change_date="Wed September 6 2023 20:09:59" location="/home/byron/ServerProjects/super6502/hw/efinix_fpga" sw_version="2022.2.322" last_run_state="pass" last_run_tool="efx_map" last_run_flow="syn" config_result_in_sync="true" design_ood="sync" place_ood="sync" route_ood="sync" xmlns:efx="http://www.efinixinc.com/enf_proj" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:schemaLocation="http://www.efinixinc.com/enf_proj enf_proj.xsd">
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<efx:device_info>
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<efx:family name="Trion"/>
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<efx:device name="T20F256"/>
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