Merge branch '32-add-build-check-to-ci' into 'master'

Resolve "Add build check to CI"

See merge request bslathi19/super6502!27

.gitlab-ci.yml

@@ -16,14 +16,31 @@
 # This specific template is located at:
 # https://gitlab.com/gitlab-org/gitlab/-/blob/master/lib/gitlab/ci/templates/Getting-Started.gitlab-ci.yml
 
+variables:
+     GIT_SUBMODULE_STRATEGY: recursive
+
 stages:          # List of stages for jobs, and their order of execution
   - build
 
-build-job:       # This job runs in the build stage, which runs first.
+build-fpga:       # This job runs in the build stage, which runs first.
   tags:
     - efinity
+    - linux
   stage: build
   script:
     - source init_env.sh
     - cd hw/efinix_fpga
     - make
+
+build-sim:
+  tags:
+   - iverilog
+   - linux
+  stage: build
+  script:  
+    - source init_env.sh
+    - cd sw/cc65
+    - make -j
+    - cd ../..
+    - cd hw/efinix_fpga/simulation
+    - make

hw/efinix_fpga/simulation/Makefile

@@ -5,9 +5,10 @@ SRCS+=$(shell find ../src/ -type f -name "*.*v")
 INC=$(shell find include/ -type f)
 
 TEST_PROGRAM_NAME?=loop_test
-
+TEST_FOLDER?=$(REPO_TOP)/sw/test_code/$(TEST_PROGRAM_NAME)
 TEST_PROGRAM?=$(REPO_TOP)/sw/test_code/$(TEST_PROGRAM_NAME)/$(TEST_PROGRAM_NAME).hex
 
+
 #TODO implement something like sources.list
 
 TOP_MODULE=sim_top
@@ -19,9 +20,10 @@ all: $(INIT_MEM)
 	iverilog -g2005-sv $(FLAGS) -s $(TOP_MODULE) -o $(TARGET) $(INC) $(SRCS)
 
 $(INIT_MEM):
+	$(MAKE) -C $(TEST_FOLDER)
 	cp $(TEST_PROGRAM) ./init_hex.mem
 
 .PHONY: clean
 clean:
 	rm -rf $(TARGET)
-	rm -rf $(INIT_MEM)
+	rm -rf $(INIT_MEM)

hw/efinix_fpga/super6502.xml

@@ -1,4 +1,4 @@
-<efx:project xmlns:efx="http://www.efinixinc.com/enf_proj" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" name="super6502" description="" last_change_date="Thu Sep 28 2023 21:28:58" location="/home/byron/ServerProjects/super6502/hw/efinix_fpga" sw_version="2023.1.150" last_run_state="pass" last_run_tool="efx_pgm" last_run_flow="bitstream" config_result_in_sync="sync" design_ood="sync" place_ood="sync" route_ood="sync" xsi:schemaLocation="http://www.efinixinc.com/enf_proj enf_proj.xsd">
+<efx:project xmlns:efx="http://www.efinixinc.com/enf_proj" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" name="super6502" description="" last_change_date="Thu Sep 28 2023 09:38:33 PM" location="/home/byron/ServerProjects/super6502/hw/efinix_fpga" sw_version="2023.1.150" last_run_state="pass" last_run_tool="efx_pgm" last_run_flow="bitstream" config_result_in_sync="sync" design_ood="sync" place_ood="sync" route_ood="sync" xsi:schemaLocation="http://www.efinixinc.com/enf_proj enf_proj.xsd">
     <efx:device_info>
         <efx:family name="Trion" />
         <efx:device name="T20F256" />