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Update RTC code test

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This commit is contained in:
Byron Lathi
2023-11-19 13:50:00 -08:00
parent 7002aeebe6
commit 7c24389b10
3 changed files with 52 additions and 4 deletions
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26
hw/efinix_fpga/simulation/tbs/rtc_code_tb.sv
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@@ -20,4 +20,30 @@ always begin
# 1;
end
localparam increment = 3;
logic [7:0] prev;
initial prev = '0;
always @(u_sim_top.w_cpu_addr) begin
if (
u_sim_top.w_cpu_addr == 16'h1 &&
u_sim_top.w_cpu_we == '1
) begin
if (u_sim_top.w_cpu_data_from_cpu <= prev) begin
$display("Value didn't increment!");
$display("Bad finish!");
$finish_and_return(-1);
end
prev = u_sim_top.w_cpu_data_from_cpu;
$display("print1: %x", u_sim_top.w_cpu_data_from_cpu);
end
end
initial begin
repeat (5000) @(posedge u_sim_top.r_clk_cpu);
$display("Timed out");
$finish_and_return(-1);
end
endmodule

6
hw/efinix_fpga/src/super6502.sv
View File

@@ -112,7 +112,7 @@ always_comb begin
w_divider_cs = w_mapped_addr >= 16'hefe8 && w_mapped_addr <= 16'hefef;
w_uart_cs = w_mapped_addr >= 16'hefe6 && w_mapped_addr <= 16'hefe7;
w_spi_cs = w_mapped_addr >= 16'hefd8 && w_mapped_addr <= 16'hefdb;
w_leds_cs = w_mapped_addr == 16'hefff;
w_leds_cs = w_mapped_addr == 16'hefd7;
w_sdram_cs = ~(
w_rom_cs |
@@ -146,7 +146,7 @@ always_comb begin
else if (w_irq_cs)
cpu_data_out = w_irq_data_out;
else if (w_rtc_cs)
cpu_data_out = w_rtc_cs;
cpu_data_out = w_rtc_data_out;
else if (w_sdram_cs)
cpu_data_out = w_sdram_data_out;
else
@@ -289,7 +289,7 @@ interrupt_controller u_interrupt_controller(
.addr(w_mapped_addr[0]),
.cs(w_irq_cs),
.rwb(cpu_rwb),
.int_in(int_in),
.int_in(w_int_in),
.int_out(w_irq)
);