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Fix clocks, define RTL_SIM

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Byron Lathi
2023-09-24 23:58:32 -07:00
parent be68b4c9f9
commit 95e05292cc
2 changed files with 4 additions and 4 deletions
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2
hw/efinix_fpga/simulation/Makefile
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@@ -13,7 +13,7 @@ TEST_PROGRAM=$(REPO_TOP)/sw/test_code/$(TEST_PROGRAM_NAME)/$(TEST_PROGRAM_NAME).
TOP_MODULE=sim_top
TARGET=sim_top
INIT_MEM=init_hex.mem
FLAGS=-DSIM
FLAGS=-DSIM -DRTL_SIM
all: $(INIT_MEM)
iverilog -g2005-sv $(FLAGS) -s $(TOP_MODULE) -o $(TARGET) $(INC) $(SRCS)