Change sdrclk and sysclk to have aligned rising edges

2023-09-24 14:53:38 -07:00
parent 3fcfa4d3ac
commit be68b4c9f9
1 changed files with 1 additions and 1 deletions
--- a/hw/efinix_fpga/simulation/src/sim_top.sv
+++ b/hw/efinix_fpga/simulation/src/sim_top.sv
@@ -16,7 +16,7 @@ end

 // clk_200
 initial begin
-	r_sdrclk <= '0;
+	r_sdrclk <= '1;
 	forever begin
 		#2.5 r_sdrclk <= ~r_sdrclk;
 	end