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Fix clocks, define RTL_SIM

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This commit is contained in:
Byron Lathi
2023-09-24 23:58:32 -07:00
parent be68b4c9f9
commit 95e05292cc
2 changed files with 4 additions and 4 deletions
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2
hw/efinix_fpga/simulation/Makefile
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@@ -13,7 +13,7 @@ TEST_PROGRAM=$(REPO_TOP)/sw/test_code/$(TEST_PROGRAM_NAME)/$(TEST_PROGRAM_NAME).
TOP_MODULE=sim_top TOP_MODULE=sim_top
TARGET=sim_top TARGET=sim_top
INIT_MEM=init_hex.mem INIT_MEM=init_hex.mem
FLAGS=-DSIM FLAGS=-DSIM -DRTL_SIM
all: $(INIT_MEM) all: $(INIT_MEM)
iverilog -g2005-sv $(FLAGS) -s $(TOP_MODULE) -o $(TARGET) $(INC) $(SRCS) iverilog -g2005-sv $(FLAGS) -s $(TOP_MODULE) -o $(TARGET) $(INC) $(SRCS)

6
hw/efinix_fpga/simulation/src/sim_top.sv
View File

@@ -24,7 +24,7 @@ end
// clk_50 // clk_50
initial begin initial begin
r_clk_50 <= '0; r_clk_50 <= '1;
forever begin forever begin
#10 r_clk_50 <= ~r_clk_50; #10 r_clk_50 <= ~r_clk_50;
end end
@@ -32,7 +32,7 @@ end
// clk_2 // clk_2
initial begin initial begin
r_clk_2 <= '0; r_clk_2 <= '1;
forever begin forever begin
#250 r_clk_2 <= ~r_clk_2; #250 r_clk_2 <= ~r_clk_2;
end end
@@ -86,7 +86,7 @@ cpu_65c02 u_cpu(
super6502 u_dut( super6502 u_dut(
.i_sysclk(r_sysclk), .i_sysclk(r_sysclk),
.i_sdrclk(r_sdrclk), .i_sdrclk(r_sdrclk),
.i_tACclk(r_sdrclk), .i_tACclk(~r_sdrclk),
.clk_50(r_clk_50), .clk_50(r_clk_50),
.clk_2(r_clk_2), .clk_2(r_clk_2),
.button_reset(button_reset), .button_reset(button_reset),