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Update submodules, update sources

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Byron Lathi
2024-03-15 21:02:53 -07:00
parent eb5c3b0b02
commit 9b50dab855
4 changed files with 7 additions and 4 deletions
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hw/super6502_fpga/src/sim/sources.list
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@@ -4,4 +4,5 @@ sub/verilog-6502/cpu_65c02.v
sub/sim_sdram/generic_sdr.v
sub/verilog-sd-emulator/src/sd_card_command.sv
sub/verilog-sd-emulator/src/sd_card_emu.sv
sub/verilog-sd-emulator/src/sd_card_state_controller.sv
sub/verilog-sd-emulator/src/sd_card_state_controller.sv
sub/verilog-sd-emulator/src/sd_card_data.sv