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Update submodules, update sources

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This commit is contained in:
Byron Lathi
2024-03-15 21:02:53 -07:00
parent eb5c3b0b02
commit 9b50dab855
4 changed files with 7 additions and 4 deletions
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4
hw/super6502_fpga/src/sim/hvl/sim_top.sv
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@@ -168,7 +168,9 @@ sd_card_emu u_sd_card_emu(
.clk(o_sd_clk), .clk(o_sd_clk),
.rst(~button_reset), .rst(~button_reset),
.i_cmd(o_sd_cmd), .i_cmd(o_sd_cmd),
.o_cmd(i_sd_cmd) .o_cmd(i_sd_cmd),
.i_dat(o_sd_dat),
.o_dat(i_sd_dat)
); );
initial begin initial begin

3
hw/super6502_fpga/src/sim/sources.list
View File

@@ -4,4 +4,5 @@ sub/verilog-6502/cpu_65c02.v
sub/sim_sdram/generic_sdr.v sub/sim_sdram/generic_sdr.v
sub/verilog-sd-emulator/src/sd_card_command.sv sub/verilog-sd-emulator/src/sd_card_command.sv
sub/verilog-sd-emulator/src/sd_card_emu.sv sub/verilog-sd-emulator/src/sd_card_emu.sv
sub/verilog-sd-emulator/src/sd_card_state_controller.sv sub/verilog-sd-emulator/src/sd_card_state_controller.sv
sub/verilog-sd-emulator/src/sd_card_data.sv

2
hw/super6502_fpga/src/sim/sub/verilog-sd-emulator

Submodule hw/super6502_fpga/src/sim/sub/verilog-sd-emulator updated: c64eff4f36...265c636c86

2
hw/super6502_fpga/src/sub/rtl-common

Submodule hw/super6502_fpga/src/sub/rtl-common updated: 14177224f6...bdf655b77b