Add bb_spi_controller

Bit banged spi controller, very simple but very slow.

.gitlab-ci.yml

@@ -23,3 +23,10 @@ test_addr_decode:
     script:
       - cd hw/fpga/simulation/modelsim/
       - vsim -do "do cs_testbench.do"
+
+test_bb_spi:
+    stage: test
+    image: bslathi19/modelsim_18.1:lite
+    script:
+      - cd hw/fpga/simulation/modelsim/
+      - vsim -do "do bb_spi_testbench.do"

hw/fpga/bb_spi_controller.sv

@@ -0,0 +1,43 @@
+module bb_spi_controller(
+    input clk,
+    input rst,
+    
+    input spi_cs,
+
+    input logic [7:0] data_in,
+    output logic [7:0] data_out,
+    
+    input rw,
+    
+    output logic SPI_SSn,
+    output logic SPI_MOSI,
+    output logic SPI_SCLK,
+    input SPI_MISO,
+    input SPI_slave_IRQ
+);
+
+logic [7:0] val;
+
+
+
+assign data_out = val;
+
+        
+assign SPI_SCLK = val[0];
+assign SPI_SSn = val[1];
+assign SPI_MOSI = val[2];
+
+always @(posedge clk) begin
+    if (rst) begin
+        val <= 8'h2;  //start with SS high
+    end
+    
+    if (spi_cs & ~rw)
+        val <= data_in;
+        
+    val[3] <= SPI_MISO;
+    val[4] <= SPI_slave_IRQ;
+end
+
+
+endmodule

hw/fpga/hvl/bb_spi_testbench.sv

@@ -0,0 +1,74 @@
+module testbench();
+
+timeunit 10ns;
+
+timeprecision 1ns;
+
+logic clk, rst, spi_cs;
+logic [7:0] data_in, data_out;
+logic rw;
+logic SPI_SSn, SPI_MOSI, SPI_SCLK, SPI_MISO;
+logic SPI_slave_IRQ;
+
+
+bb_spi_controller dut(.*);
+
+always #5 clk = clk === 1'b0;
+
+task write_byte(input logic [8:0] wdata);
+    for (int i = 0; i < 8; i++) begin
+        write_bit(8'b0 + (wdata[i] << 2));
+        write_bit(8'b1 + (wdata[i] << 2));
+    end
+    write_bit(8'b0);
+endtask
+
+task write_bit(input logic [8:0] wdata);
+    @(negedge clk);
+    spi_cs <= '1;
+    data_in <= wdata;
+    rw <= '0;
+    @(posedge clk);
+endtask
+
+task read(output logic [8:0] rdata);
+    @(negedge clk);
+    spi_cs <= '1;
+    rdata <= data_out;
+    rw <= '1;
+    @(posedge clk);
+endtask
+
+always @(posedge SPI_SCLK) begin
+    assert(SPI_MOSI == data_in[2]) else begin
+        $error("SPI_MOSI data error");
+    end
+end
+
+initial begin : TEST_VECTORS
+    SPI_slave_IRQ <= '0;
+    SPI_MISO <= '0;
+
+    rst <= '1;
+    repeat(5) @(posedge clk);
+    rst <= '0;
+    @(posedge clk);
+    
+    write_byte(8'ha5);
+
+    repeat(5) @(posedge clk);
+
+    SPI_slave_IRQ <= '1;
+    @(posedge clk);
+    @(posedge clk);
+    assert (data_out[4] == '1) else begin
+        $error("IRQ expected");
+    end
+
+    repeat(5) @(posedge clk);
+
+    $finish();
+
+end
+
+endmodule

hw/fpga/simulation/modelsim/bb_spi_testbench.do

@@ -0,0 +1,24 @@
+transcript on
+if {[file exists rtl_work]} {
+	vdel -lib rtl_work -all
+}
+vlib rtl_work
+vmap work rtl_work
+
+vlog -sv -work work  {../../bb_spi_controller.sv}
+vlog -sv -work work  {../../hvl/bb_spi_testbench.sv}
+
+vsim -t 1ps -L altera_ver -L lpm_ver -L sgate_ver -L altera_mf_ver -L altera_lnsim_ver -L stratixv_ver -L stratixv_hssi_ver -L stratixv_pcie_hip_ver -L rtl_work -L work -voptargs="+acc"  testbench
+
+add wave -group {dut} -radix hexadecimal sim:/testbench/dut/*
+
+onfinish stop
+run -all
+
+if { [coverage attribute -name TESTSTATUS -concise] == "1"} {
+    echo Warning
+    quit -f -code 0
+}
+
+quit -code [coverage attribute -name TESTSTATUS -concise]
+

hw/fpga/super6502.qsf

@@ -49,7 +49,6 @@ set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 256
 set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (SystemVerilog)"
 set_global_assignment -name EDA_TIME_SCALE "1 ps" -section_id eda_simulation
 set_global_assignment -name EDA_OUTPUT_DATA_FORMAT "SYSTEMVERILOG HDL" -section_id eda_simulation
-set_global_assignment -name SYSTEMVERILOG_FILE super6502.sv
 set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
 set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
 set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
@@ -91,7 +90,11 @@ set_location_assignment PIN_W7 -to cpu_mlb
 set_location_assignment PIN_W8 -to cpu_irqb
 set_location_assignment PIN_P11 -to clk
 set_location_assignment PIN_B8 -to rst
+set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
+set_global_assignment -name SYSTEMVERILOG_FILE bb_spi_controller.sv
+set_global_assignment -name SYSTEMVERILOG_FILE super6502.sv
 set_global_assignment -name QIP_FILE ram.qip
 set_global_assignment -name SDC_FILE super6502.sdc
 set_global_assignment -name QIP_FILE rom.qip
-set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
+set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
+set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"