First stab at getting sdram working

2022-12-22 20:25:32 -05:00
parent 772f8ff13f
commit cf9aef64ac
14 changed files with 8487 additions and 392 deletions
--- a/hw/efinix_fpga/ip/sdram_controller/settings.json
+++ b/hw/efinix_fpga/ip/sdram_controller/settings.json
@@ -0,0 +1,44 @@
+{
+    "args": [
+        "-o",
+        "sdram_controller",
+        "--base_path",
+        "/home/byron/Projects/super6502/hw/efinix_fpga/ip",
+        "--vlnv",
+        {
+            "vendor": "efinixinc.com",
+            "library": "memory_controller",
+            "name": "efx_sdram_controller",
+            "version": "1.6"
+        }
+    ],
+    "conf": {
+        "fCK_MHz": "200",
+        "tIORT_u": "2",
+        "CL": "3",
+        "DDIO_TYPE": "0",
+        "DQ_GROUP": "2",
+        "ROW_WIDTH": "13",
+        "COL_WIDTH": "9",
+        "tPWRUP": "200000",
+        "tRAS": "44",
+        "tRAS_MAX": "120000",
+        "tRC": "66",
+        "tRCD": "20",
+        "tREF": "64000000",
+        "tRFC ": "66",
+        "tRP": "20",
+        "SDRAM_MODE": "0",
+        "DATA_RATE": "2"
+    },
+    "output": {
+        "external_source": [
+            "/home/byron/Projects/super6502/hw/efinix_fpga/ip/sdram_controller/sdram_controller.v",
+            "/home/byron/Projects/super6502/hw/efinix_fpga/ip/sdram_controller/sdram_controller_tmpl.v",
+            "/home/byron/Projects/super6502/hw/efinix_fpga/ip/sdram_controller/sdram_controller_define.vh",
+            "/home/byron/Projects/super6502/hw/efinix_fpga/ip/sdram_controller/sdram_controller_tmpl.vhd"
+        ]
+    },
+    "sw_version": "2022.1.226",
+    "generated_date": "2022-12-22T03:56:49.168890"
+}