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First stab at getting sdram working

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This commit is contained in:
Byron Lathi
2022-12-22 20:25:32 -05:00
parent 772f8ff13f
commit cf9aef64ac
14 changed files with 8487 additions and 392 deletions
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4
hw/efinix_fpga/addr_decode.sv
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@@ -3,10 +3,12 @@ module addr_decode
input [15:0] i_addr,
output o_rom_cs,
output o_leds_cs
output o_leds_cs,
output o_sdram_cs
);
assign o_rom_cs = i_addr >= 16'hf000 && i_addr <= 16'hffff;
assign o_leds_cs = i_addr == 16'hefff;
assign o_sdram_cs = i_addr < 16'h8000;
endmodule

3385
hw/efinix_fpga/debug_profile.wizard.json
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File diff suppressed because it is too large Load Diff

8
hw/efinix_fpga/ip/bram/bram_ini.vh
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@@ -4,10 +4,10 @@ input integer index;//Mode type
input integer val_; //Port A index, Port B Index, Number of Items in Loop, Port A Start, Port B Start, reserved
case (index)
0: bram_ini_table=
(val_== 0)?256'h00000000000000000fe00080000fa000d00003a000ef000ff0008d000ff000a9:
(val_== 1)?256'h0000000000000000000000000000000000000000000000000000000000000000:
(val_== 2)?256'h0000000000000000000000000000000000000000000000000000000000000000:
(val_== 3)?256'h0000000000000000000000000000000000000000000000000000000000000000:
(val_== 0)?256'h00ea000ea000ea000ea00010000040008d0003a00010000000008d000ff000a9:
(val_== 1)?256'h01000004000cd0001000000000ad000ea000ea000ea000ea000ea000ea000ea0:
(val_== 2)?256'hff0008d000f0000a9000f900080000ef000ff0008d00001000a900007000f000:
(val_== 3)?256'h0000000000000000000000000000000000000000000000000f900080000ef000:
(val_== 4)?256'h0000000000000000000000000000000000000000000000000000000000000000:
(val_== 5)?256'h0000000000000000000000000000000000000000000000000000000000000000:
(val_== 6)?256'h0000000000000000000000000000000000000000000000000000000000000000:

82
hw/efinix_fpga/ip/bram/init_hex.mem
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@@ -1,45 +1,45 @@
a9
ff
8d
ff
ef
3a
d0
fa
A9
FF
8D
00
10
3A
8D
04
10
EA
EA
EA
EA
EA
EA
EA
EA
EA
EA
EA
AD
00
10
CD
04
10
F0
07
A9
01
8D
FF
EF
80
fe
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
F9
A9
F0
8D
FF
EF
80
F9
00
00
00

4261
hw/efinix_fpga/ip/sdram_controller/sdram_controller.v Normal file
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File diff suppressed because it is too large Load Diff

80
hw/efinix_fpga/ip/sdram_controller/sdram_controller_define.vh Normal file
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@@ -0,0 +1,80 @@
// =============================================================================
// Generated by efx_ipmgr
// Version: 2022.1.226
// IP Version: 1.6
// =============================================================================
////////////////////////////////////////////////////////////////////////////////
// Copyright (C) 2013-2022 Efinix Inc. All rights reserved.
//
// This document contains proprietary information which is
// protected by copyright. All rights are reserved. This notice
// refers to original work by Efinix, Inc. which may be derivitive
// of other work distributed under license of the authors. In the
// case of derivative work, nothing in this notice overrides the
// original author's license agreement. Where applicable, the
// original license agreement is included in it's original
// unmodified form immediately below this header.
//
// WARRANTY DISCLAIMER.
// THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND
// EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH
// RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES,
// INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF
// MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR
// PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED
// WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE.
//
// LIMITATION OF LIABILITY.
// NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY
// INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT
// MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY
// OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT,
// SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY
// CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF
// GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR
// MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN
// THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER
// (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE
// BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO
// NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR
// CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT
// APPLY TO LICENSEE.
//
////////////////////////////////////////////////////////////////////////////////
localparam fSYS_MHz = 100;
localparam fCK_MHz = 200;
localparam tIORT_u = 2;
localparam BL = 1;
localparam DDIO_TYPE = "SOFT";
localparam DQ_WIDTH = 8;
localparam DQ_GROUP = 2;
localparam BA_WIDTH = 2;
localparam ROW_WIDTH = 13;
localparam COL_WIDTH = 9;
localparam tPWRUP = 200000;
localparam tRAS = 44;
localparam tRC = 66;
localparam tRCD = 20;
localparam tREF = 64000000;
localparam tWR = 2;
localparam tMRD = 2;
localparam tRFC = 66;
localparam tRAS_MAX = 120000;
localparam DATA_RATE = 2;
localparam AXI_ARADDR_WIDTH = 24;
localparam SDRAM_MODE = "Native";
localparam AXI_BUSER_WIDTH = 2;
localparam AXI_BID_WIDTH = 4;
localparam AXI_AWUSER_WIDTH = 2;
localparam AXI_AWID_WIDTH = 4;
localparam AXI_AWADDR_WIDTH = 24;
localparam AXI_RDATA_WIDTH = 32;
localparam AXI_WUSER_WIDTH = 2;
localparam AXI_WDATA_WIDTH = 32;
localparam AXI_RUSER_WIDTH = 3;
localparam AXI_ARUSER_WIDTH = 3;
localparam AXI_ARID_WIDTH = 4;
localparam tRP = 20;
localparam CL = 3;

84
hw/efinix_fpga/ip/sdram_controller/sdram_controller_tmpl.v Normal file
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@@ -0,0 +1,84 @@
////////////////////////////////////////////////////////////////////////////////
// Copyright (C) 2013-2022 Efinix Inc. All rights reserved.
//
// This document contains proprietary information which is
// protected by copyright. All rights are reserved. This notice
// refers to original work by Efinix, Inc. which may be derivitive
// of other work distributed under license of the authors. In the
// case of derivative work, nothing in this notice overrides the
// original author's license agreement. Where applicable, the
// original license agreement is included in it's original
// unmodified form immediately below this header.
//
// WARRANTY DISCLAIMER.
// THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND
// EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH
// RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES,
// INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF
// MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR
// PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED
// WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE.
//
// LIMITATION OF LIABILITY.
// NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY
// INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT
// MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY
// OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT,
// SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY
// CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF
// GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR
// MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN
// THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER
// (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE
// BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO
// NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR
// CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT
// APPLY TO LICENSEE.
//
////////////////////////////////////////////////////////////////////////////////
sdram_controller u_sdram_controller(
.i_we ( i_we ),
.i_sysclk ( i_sysclk ),
.i_arst ( i_arst ),
.i_sdrclk ( i_sdrclk ),
.i_tACclk ( i_tACclk ),
.i_pll_locked ( i_pll_locked ),
.i_re ( i_re ),
.i_last ( i_last ),
.o_dbg_tRTW_done ( o_dbg_tRTW_done ),
.o_dbg_ref_req ( o_dbg_ref_req ),
.o_dbg_wr_ack ( o_dbg_wr_ack ),
.o_dbg_rd_ack ( o_dbg_rd_ack ),
.o_dbg_n_CS ( o_dbg_n_CS ),
.o_dbg_n_RAS ( o_dbg_n_RAS ),
.o_dbg_n_CAS ( o_dbg_n_CAS ),
.o_dbg_n_WE ( o_dbg_n_WE ),
.o_dbg_BA ( o_dbg_BA ),
.o_dbg_ADDR ( o_dbg_ADDR ),
.o_dbg_DATA_out ( o_dbg_DATA_out ),
.o_dbg_DATA_in ( o_dbg_DATA_in ),
.i_addr ( i_addr ),
.i_din ( i_din ),
.i_dm ( i_dm ),
.o_dout ( o_dout ),
.o_sdr_state ( o_sdr_state ),
.o_sdr_init_done ( o_sdr_init_done ),
.o_wr_ack ( o_wr_ack ),
.o_rd_ack ( o_rd_ack ),
.o_ref_req ( o_ref_req ),
.o_rd_valid ( o_rd_valid ),
.o_sdr_CKE ( o_sdr_CKE ),
.o_sdr_n_CS ( o_sdr_n_CS ),
.o_sdr_n_RAS ( o_sdr_n_RAS ),
.o_sdr_n_CAS ( o_sdr_n_CAS ),
.o_sdr_n_WE ( o_sdr_n_WE ),
.o_sdr_BA ( o_sdr_BA ),
.o_sdr_ADDR ( o_sdr_ADDR ),
.o_sdr_DATA ( o_sdr_DATA ),
.o_sdr_DATA_oe ( o_sdr_DATA_oe ),
.i_sdr_DATA ( i_sdr_DATA ),
.o_sdr_DQM ( o_sdr_DQM ),
.o_dbg_dly_cnt_b ( o_dbg_dly_cnt_b ),
.o_dbg_tRCD_done ( o_dbg_tRCD_done )
);

134
hw/efinix_fpga/ip/sdram_controller/sdram_controller_tmpl.vhd Normal file
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@@ -0,0 +1,134 @@
////////////////////////////////////////////////////////////////////////////////
// Copyright (C) 2013-2022 Efinix Inc. All rights reserved.
//
// This document contains proprietary information which is
// protected by copyright. All rights are reserved. This notice
// refers to original work by Efinix, Inc. which may be derivitive
// of other work distributed under license of the authors. In the
// case of derivative work, nothing in this notice overrides the
// original author's license agreement. Where applicable, the
// original license agreement is included in it's original
// unmodified form immediately below this header.
//
// WARRANTY DISCLAIMER.
// THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND
// EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH
// RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES,
// INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF
// MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR
// PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED
// WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE.
//
// LIMITATION OF LIABILITY.
// NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY
// INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT
// MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY
// OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT,
// SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY
// CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF
// GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR
// MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN
// THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER
// (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE
// BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO
// NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR
// CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT
// APPLY TO LICENSEE.
//
////////////////////////////////////////////////////////////////////////////////
------------- Begin Cut here for COMPONENT Declaration ------
COMPONENT sdram_controller is
PORT (
i_we : in std_logic;
i_sysclk : in std_logic;
i_arst : in std_logic;
i_sdrclk : in std_logic;
i_tACclk : in std_logic;
i_pll_locked : in std_logic;
i_re : in std_logic;
i_last : in std_logic;
o_dbg_tRTW_done : out std_logic;
o_dbg_ref_req : out std_logic;
o_dbg_wr_ack : out std_logic;
o_dbg_rd_ack : out std_logic;
o_dbg_n_CS : out std_logic_vector(1 downto 0);
o_dbg_n_RAS : out std_logic_vector(1 downto 0);
o_dbg_n_CAS : out std_logic_vector(1 downto 0);
o_dbg_n_WE : out std_logic_vector(1 downto 0);
o_dbg_BA : out std_logic_vector(3 downto 0);
o_dbg_ADDR : out std_logic_vector(25 downto 0);
o_dbg_DATA_out : out std_logic_vector(31 downto 0);
o_dbg_DATA_in : out std_logic_vector(31 downto 0);
i_addr : in std_logic_vector(23 downto 0);
i_din : in std_logic_vector(31 downto 0);
i_dm : in std_logic_vector(3 downto 0);
o_dout : out std_logic_vector(31 downto 0);
o_sdr_state : out std_logic_vector(3 downto 0);
o_sdr_init_done : out std_logic;
o_wr_ack : out std_logic;
o_rd_ack : out std_logic;
o_ref_req : out std_logic;
o_rd_valid : out std_logic;
o_sdr_CKE : out std_logic_vector(1 downto 0);
o_sdr_n_CS : out std_logic_vector(1 downto 0);
o_sdr_n_RAS : out std_logic_vector(1 downto 0);
o_sdr_n_CAS : out std_logic_vector(1 downto 0);
o_sdr_n_WE : out std_logic_vector(1 downto 0);
o_sdr_BA : out std_logic_vector(3 downto 0);
o_sdr_ADDR : out std_logic_vector(25 downto 0);
o_sdr_DATA : out std_logic_vector(31 downto 0);
o_sdr_DATA_oe : out std_logic_vector(31 downto 0);
i_sdr_DATA : in std_logic_vector(31 downto 0);
o_sdr_DQM : out std_logic_vector(3 downto 0);
o_dbg_dly_cnt_b : out std_logic_vector(5 downto 0);
o_dbg_tRCD_done : out std_logic);
END COMPONENT;
---------------------- End COMPONENT Declaration ------------
------------- Begin Cut here for INSTANTIATION Template -----
u_sdram_controller : sdram_controller
PORT MAP (
i_we => i_we,
i_sysclk => i_sysclk,
i_arst => i_arst,
i_sdrclk => i_sdrclk,
i_tACclk => i_tACclk,
i_pll_locked => i_pll_locked,
i_re => i_re,
i_last => i_last,
o_dbg_tRTW_done => o_dbg_tRTW_done,
o_dbg_ref_req => o_dbg_ref_req,
o_dbg_wr_ack => o_dbg_wr_ack,
o_dbg_rd_ack => o_dbg_rd_ack,
o_dbg_n_CS => o_dbg_n_CS,
o_dbg_n_RAS => o_dbg_n_RAS,
o_dbg_n_CAS => o_dbg_n_CAS,
o_dbg_n_WE => o_dbg_n_WE,
o_dbg_BA => o_dbg_BA,
o_dbg_ADDR => o_dbg_ADDR,
o_dbg_DATA_out => o_dbg_DATA_out,
o_dbg_DATA_in => o_dbg_DATA_in,
i_addr => i_addr,
i_din => i_din,
i_dm => i_dm,
o_dout => o_dout,
o_sdr_state => o_sdr_state,
o_sdr_init_done => o_sdr_init_done,
o_wr_ack => o_wr_ack,
o_rd_ack => o_rd_ack,
o_ref_req => o_ref_req,
o_rd_valid => o_rd_valid,
o_sdr_CKE => o_sdr_CKE,
o_sdr_n_CS => o_sdr_n_CS,
o_sdr_n_RAS => o_sdr_n_RAS,
o_sdr_n_CAS => o_sdr_n_CAS,
o_sdr_n_WE => o_sdr_n_WE,
o_sdr_BA => o_sdr_BA,
o_sdr_ADDR => o_sdr_ADDR,
o_sdr_DATA => o_sdr_DATA,
o_sdr_DATA_oe => o_sdr_DATA_oe,
i_sdr_DATA => i_sdr_DATA,
o_sdr_DQM => o_sdr_DQM,
o_dbg_dly_cnt_b => o_dbg_dly_cnt_b,
o_dbg_tRCD_done => o_dbg_tRCD_done);
------------------------ End INSTANTIATION Template ---------

44
hw/efinix_fpga/ip/sdram_controller/settings.json Normal file
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@@ -0,0 +1,44 @@
{
"args": [
"-o",
"sdram_controller",
"--base_path",
"/home/byron/Projects/super6502/hw/efinix_fpga/ip",
"--vlnv",
{
"vendor": "efinixinc.com",
"library": "memory_controller",
"name": "efx_sdram_controller",
"version": "1.6"
}
],
"conf": {
"fCK_MHz": "200",
"tIORT_u": "2",
"CL": "3",
"DDIO_TYPE": "0",
"DQ_GROUP": "2",
"ROW_WIDTH": "13",
"COL_WIDTH": "9",
"tPWRUP": "200000",
"tRAS": "44",
"tRAS_MAX": "120000",
"tRC": "66",
"tRCD": "20",
"tREF": "64000000",
"tRFC ": "66",
"tRP": "20",
"SDRAM_MODE": "0",
"DATA_RATE": "2"
},
"output": {
"external_source": [
"/home/byron/Projects/super6502/hw/efinix_fpga/ip/sdram_controller/sdram_controller.v",
"/home/byron/Projects/super6502/hw/efinix_fpga/ip/sdram_controller/sdram_controller_tmpl.v",
"/home/byron/Projects/super6502/hw/efinix_fpga/ip/sdram_controller/sdram_controller_define.vh",
"/home/byron/Projects/super6502/hw/efinix_fpga/ip/sdram_controller/sdram_controller_tmpl.vhd"
]
},
"sw_version": "2022.1.226",
"generated_date": "2022-12-22T03:56:49.168890"
}

273
hw/efinix_fpga/sdram_adapter.sv Normal file
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@@ -0,0 +1,273 @@
module sdram_adapter(
input logic i_cpuclk,
input logic i_arst, // Async Reset
input logic i_sysclk, // Controller Clock (100MHz)
input logic i_sdrclk, // t_su and t_wd clock (200MHz)
input logic i_tACclk, // t_ac clock (200MHz)
input logic i_cs, // Chip select
input logic i_rwb, // Read/Write. Write is low
input logic [24:0] i_addr, // Input address. Byte addressed
input logic [7:0] i_data, // Input Data
output logic [7:0] o_data, // Output data
output o_sdr_init_done,
output o_sdr_CKE,
output o_sdr_n_CS,
output o_sdr_n_RAS,
output o_sdr_n_CAS,
output o_sdr_n_WE,
output [1:0] o_sdr_BA,
output [12:0] o_sdr_ADDR,
output [15:0] o_sdr_DATA,
output [15:0] o_sdr_DATA_oe,
input [15:0] i_sdr_DATA,
output [1:0] o_sdr_DQM
);
logic [1:0] w_sdr_CKE;
logic [1:0] w_sdr_n_CS;
logic [1:0] w_sdr_n_RAS;
logic [1:0] w_sdr_n_CAS;
logic [1:0] w_sdr_n_WE;
logic [3:0] w_sdr_BA;
logic [25:0] w_sdr_ADDR;
logic [31:0] w_sdr_DATA;
logic [31:0] w_sdr_DATA_oe;
logic [3:0] w_sdr_DQM;
assign o_sdr_CKE = w_sdr_CKE[0]; //Using SOFT ddio, ignore second cycle
assign o_sdr_n_CS = w_sdr_n_CS[0];
assign o_sdr_n_RAS = w_sdr_n_RAS[0];
assign o_sdr_n_CAS = w_sdr_n_CAS[0];
assign o_sdr_n_WE = w_sdr_n_WE[0];
assign o_sdr_BA = w_sdr_BA[0+:2];
assign o_sdr_ADDR = w_sdr_ADDR[0+:13];
assign o_sdr_DATA = w_sdr_DATA[0+:16];
assign o_sdr_DATA_oe = w_sdr_DATA_oe[0+:16];
assign o_sdr_DQM = w_sdr_DQM[0+:2];
// What should happen when the cpu writes something?
// 1. Address should already be calculated from the memory mapper, don't need to worry about it
// 2. Data byte position needs to be determined. Each write is 32 bits, so the dm bits need to
// be set and the byte shifted to the correct position
// 3. write enable and last should be set high. Only ever do bursts of 1.
// 4. Sample wr_ack and when it goes high, release write_enable and last
// What should happen when the cpu reads something?
// 1. Address should already be calculated from the memory mapper, don't need to worry about it
// 2. read_enable and last should be set high. Only ever to bursts of 1.
// 3. Sample rd_ack and when it goes high, release read_enable and last
// 4. Sample read_valid signal. When it is high, grab the data on the on the bus.
// The returned data will be 16 bit, so you need to extract the correct byte. (or will it be 32?)
// when writing, the write data is only valid on a falling edge.
// Really all of this should be done on falling edges.
// But basically if we are in access, and cpuclk goes low, go back to wait.
// If something actually happened, we would be in one of the read/write states.
enum bit [1:0] {ACCESS, READ_WAIT, WRITE_WAIT, WAIT} state, next_state;
logic w_read, w_write, w_last;
logic [23:0] w_addr, r_addr;
logic [31:0] w_data_i, w_data_o;
logic [3:0] w_dm, r_dm;
logic w_wr_ack, w_rd_ack, w_rd_valid;
logic [7:0] data, _data;
logic w_data_valid;
logic [31:0] r_write_data;
logic [1:0] counter, next_counter;
always @(posedge i_sysclk) begin
if (i_arst) begin
state <= WAIT;
counter <= '0;
end else begin
state <= next_state;
counter <= next_counter;
r_write_data <= w_data_i;
r_addr <= w_addr;
r_dm <= w_dm;
end
if (w_data_valid)
o_data <= _data;
end
//because of timing issues, We really need to trigger
//the write on the falling edge of phi2. There is a 2ns
//delay between the rising edge of phi2 and data valid
//Since the address is valid on the previous falling edge,
//Reads can occur on the rising edge I guess.
//so basically cpu clock goes high when cs goes high we go into a priming state
//where we wait until cs goes low. when cpu clock is low, do the actual write.
//in terms of the existing state, the access state needs to only do something
//if selected AND cpu_clock is low. If cpu clock is high, we should be in wait,
//and after the read/write is complete we should also go back to wait.
//actually that may only apply to writes, since reads should occur at the rising
//edge of i_cpuclk
//Starts out in state 0 with cpuclk low and cs high.
//Then, cpuclk goes high. This is now a valid time to read
//After this, cpuclk goes low again, this is now a valid time to write.
//so basically if cpuclk goes low when cs is low, go to wait state
//what I am thinking is basically 2 states like before. wait and access.
//we go to access when cpuclk is high and cs is high.
//we can read as soon as we want if rwn is high.
//BUT if rwb is low then we have to wait untl cpuclk goes low again.
always_comb begin
next_state = state;
next_counter = counter;
w_addr = '0;
w_dm = '0;
w_read = '0;
w_write = '0;
w_last = '0;
w_data_i = '0;
w_data_valid = '0;
_data = 0;
unique case (state)
WAIT: begin
if (i_cs & i_cpuclk)
next_state = ACCESS;
end
ACCESS: begin
// only do something if selected
if (i_cs) begin
w_addr = {{i_addr[24:2]}, {1'b0}};; // divide by 2, set last bit to 0
if (i_rwb) begin //read
w_read = '1;
w_last = '1;
// dm is not needed for reads?
if (w_rd_ack) next_state = READ_WAIT;
end else begin //write
//w_data_i = i_data << (8*i_addr[1:0]);
w_data_i = {4{i_data}}; //does anything get through?
w_dm = ~(4'b1 << i_addr[1:0]);
if (~i_cpuclk) begin
w_write = '1;
w_last = '1;
next_state = WRITE_WAIT;
end
end
end
end
WRITE_WAIT: begin
// stay in this state until write is acknowledged.
w_write = '1;
w_last = '1;
w_data_i = r_write_data;
w_dm = r_dm;
w_addr = r_addr;
if (w_wr_ack) next_state = WAIT;
end
READ_WAIT: begin
if (w_rd_valid) begin
w_data_valid = '1;
_data = w_data_o[8*i_addr[1:0]+:8];
end
// you must wait until the next cycle!
if (~i_cpuclk) begin
next_state = WAIT;
end
end
endcase
end
//this seems scuffed
logic [23:0] addr_mux_out;
always_comb begin
if (state == ACCESS) begin
addr_mux_out = w_addr;
end else begin
addr_mux_out = r_addr;
end
end
logic o_dbg_tRTW_done;
logic o_dbg_ref_req;
logic o_dbg_wr_ack;
logic o_dbg_rd_ack;
logic [1:0] o_dbg_n_CS;
logic [1:0] o_dbg_n_RAS;
logic [1:0] o_dbg_n_CAS;
logic [1:0] o_dbg_n_WE;
logic [3:0] o_dbg_BA;
logic [25:0] o_dbg_ADDR;
logic [31:0] o_dbg_DATA_out;
logic [31:0] o_dbg_DATA_in;
logic o_sdr_init_done;
logic [3:0] o_sdr_state;
sdram_controller u_sdram_controller(
.i_arst(i_arst), //Positive Controller Reset
.i_sysclk(i_sysclk), //Controller Clock (100MHz)
.i_sdrclk(i_sdrclk), //t_su and t_ac clock. Double sysclk (200MHz)
.i_tACclk(i_tACclk), //t_ac clock. Also double sysclk, but different pll for tuning
.i_pll_locked(1'b1), //There exists a pll locked output from the pll, not sure why they don't use it.
.i_we(w_write), //Write enable. Can only be de-asserted if i_last is asserted and o_wr_ack is sampled high.
.i_re(w_read), //Read enable. Can only be de-asserted if i_last is asserted and o_rd_ack is sampled high.
.i_last(w_last), //Set to high to indicate the last transfer of a burst write or read.
.i_addr(addr_mux_out), //SDRAM physical address B R C. For half rate, only even addresses.
.i_din(r_write_data), //Data to write to SDRAM. Twice normal width when running at half speed (hence the even addresses)
.i_dm('0), //dm (r_dm)
.o_dout(w_data_o), //Data read from SDRAM, doubled as above.
.o_sdr_init_done(o_sdr_init_done), //Indicates that the SDRAM initialization is done.
.o_wr_ack(w_wr_ack), //Write acknowledge, handshake with we
.o_rd_ack(w_rd_ack), //Read acknowledge, handshake with re
.o_rd_valid(w_rd_valid),//Read valid. The data on o_dout is valid
.o_sdr_CKE(w_sdr_CKE),
.o_sdr_n_CS(w_sdr_n_CS),
.o_sdr_n_RAS(w_sdr_n_RAS),
.o_sdr_n_CAS(w_sdr_n_CAS),
.o_sdr_n_WE(w_sdr_n_WE),
.o_sdr_BA(w_sdr_BA),
.o_sdr_ADDR(w_sdr_ADDR),
.o_sdr_DATA(w_sdr_DATA),
.o_sdr_DATA_oe(w_sdr_DATA_oe),
.i_sdr_DATA({{16'b0}, {i_sdr_DATA}}),
.o_sdr_DQM(w_sdr_DQM),
//Does include debug signals.
.o_sdr_state(o_sdr_state),
.o_dbg_tRTW_done ( o_dbg_tRTW_done ),
.o_dbg_ref_req ( o_dbg_ref_req ),
.o_dbg_wr_ack ( o_dbg_wr_ack ),
.o_dbg_rd_ack ( o_dbg_rd_ack ),
.o_dbg_n_CS ( o_dbg_n_CS ),
.o_dbg_n_RAS ( o_dbg_n_RAS ),
.o_dbg_n_CAS ( o_dbg_n_CAS ),
.o_dbg_n_WE ( o_dbg_n_WE ),
.o_dbg_BA ( o_dbg_BA ),
.o_dbg_ADDR ( o_dbg_ADDR ),
.o_dbg_DATA_out ( o_dbg_DATA_out ),
.o_dbg_DATA_in ( o_dbg_DATA_in )
);
endmodule

169
hw/efinix_fpga/super6502.peri.xml
View File

@@ -1,5 +1,5 @@
<?xml version="1.0" encoding="UTF-8"?>
<efxpt:design_db name="super6502" device_def="T20F256" location="/home/byron/Projects/super6502/hw/efinix_fpga" version="2022.1.226" db_version="20221999" last_change_date="Tue Dec 20 17:56:46 2022" xmlns:efxpt="http://www.efinixinc.com/peri_design_db" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:schemaLocation="http://www.efinixinc.com/peri_design_db peri_design_db.xsd ">
<efxpt:design_db name="super6502" device_def="T20F256" location="/home/byron/Projects/super6502/hw/efinix_fpga" version="2022.1.226" db_version="20221999" last_change_date="Thu Dec 22 20:19:31 2022" xmlns:efxpt="http://www.efinixinc.com/peri_design_db" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:schemaLocation="http://www.efinixinc.com/peri_design_db peri_design_db.xsd ">
<efxpt:device_info>
<efxpt:iobank_info>
<efxpt:iobank name="1A" iostd="3.3 V LVTTL / LVCMOS"/>
@@ -130,6 +130,86 @@
<efxpt:gpio name="cpu_sync" gpio_def="GPIOL_67" mode="input" bus_name="" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
<efxpt:input_config name="cpu_sync" name_ddio_lo="" conn_type="normal" is_register="false" clock_name="" is_clock_inverted="false" pull_option="none" is_schmitt_trigger="false" ddio_type="none"/>
</efxpt:gpio>
<efxpt:gpio name="io_sdr_DATA[0]" gpio_def="GPIOR_92" mode="inout" bus_name="io_sdr_DATA" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
<efxpt:input_config name="i_sdr_DATA[0]" name_ddio_lo="" conn_type="normal" is_register="true" clock_name="i_sdrclk" is_clock_inverted="false" pull_option="none" is_schmitt_trigger="false" ddio_type="none"/>
<efxpt:output_config name="o_sdr_DATA[0]" name_ddio_lo="" register_option="register" clock_name="i_sdrclk" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" drive_strength="3"/>
<efxpt:output_enable_config name="o_sdr_DATA_oe[0]" is_register="true" clock_name="i_sdrclk" is_clock_inverted="false"/>
</efxpt:gpio>
<efxpt:gpio name="io_sdr_DATA[10]" gpio_def="GPIOR_116" mode="inout" bus_name="io_sdr_DATA" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
<efxpt:input_config name="i_sdr_DATA[10]" name_ddio_lo="" conn_type="normal" is_register="true" clock_name="i_sdrclk" is_clock_inverted="false" pull_option="none" is_schmitt_trigger="false" ddio_type="none"/>
<efxpt:output_config name="o_sdr_DATA[10]" name_ddio_lo="" register_option="register" clock_name="i_sdrclk" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" drive_strength="3"/>
<efxpt:output_enable_config name="o_sdr_DATA_oe[10]" is_register="true" clock_name="i_sdrclk" is_clock_inverted="false"/>
</efxpt:gpio>
<efxpt:gpio name="io_sdr_DATA[11]" gpio_def="GPIOR_108" mode="inout" bus_name="io_sdr_DATA" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
<efxpt:input_config name="i_sdr_DATA[11]" name_ddio_lo="" conn_type="normal" is_register="true" clock_name="i_sdrclk" is_clock_inverted="false" pull_option="none" is_schmitt_trigger="false" ddio_type="none"/>
<efxpt:output_config name="o_sdr_DATA[11]" name_ddio_lo="" register_option="register" clock_name="i_sdrclk" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" drive_strength="3"/>
<efxpt:output_enable_config name="o_sdr_DATA_oe[11]" is_register="true" clock_name="i_sdrclk" is_clock_inverted="false"/>
</efxpt:gpio>
<efxpt:gpio name="io_sdr_DATA[12]" gpio_def="GPIOR_112" mode="inout" bus_name="io_sdr_DATA" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
<efxpt:input_config name="i_sdr_DATA[12]" name_ddio_lo="" conn_type="normal" is_register="true" clock_name="i_sdrclk" is_clock_inverted="false" pull_option="none" is_schmitt_trigger="false" ddio_type="none"/>
<efxpt:output_config name="o_sdr_DATA[12]" name_ddio_lo="" register_option="register" clock_name="i_sdrclk" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" drive_strength="3"/>
<efxpt:output_enable_config name="o_sdr_DATA_oe[12]" is_register="true" clock_name="i_sdrclk" is_clock_inverted="false"/>
</efxpt:gpio>
<efxpt:gpio name="io_sdr_DATA[13]" gpio_def="GPIOR_106" mode="inout" bus_name="io_sdr_DATA" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
<efxpt:input_config name="i_sdr_DATA[13]" name_ddio_lo="" conn_type="normal" is_register="true" clock_name="i_sdrclk" is_clock_inverted="false" pull_option="none" is_schmitt_trigger="false" ddio_type="none"/>
<efxpt:output_config name="o_sdr_DATA[13]" name_ddio_lo="" register_option="register" clock_name="i_sdrclk" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" drive_strength="3"/>
<efxpt:output_enable_config name="o_sdr_DATA_oe[13]" is_register="true" clock_name="i_sdrclk" is_clock_inverted="false"/>
</efxpt:gpio>
<efxpt:gpio name="io_sdr_DATA[14]" gpio_def="GPIOR_98" mode="inout" bus_name="io_sdr_DATA" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
<efxpt:input_config name="i_sdr_DATA[14]" name_ddio_lo="" conn_type="normal" is_register="true" clock_name="i_sdrclk" is_clock_inverted="false" pull_option="none" is_schmitt_trigger="false" ddio_type="none"/>
<efxpt:output_config name="o_sdr_DATA[14]" name_ddio_lo="" register_option="register" clock_name="i_sdrclk" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" drive_strength="3"/>
<efxpt:output_enable_config name="o_sdr_DATA_oe[14]" is_register="true" clock_name="i_sdrclk" is_clock_inverted="false"/>
</efxpt:gpio>
<efxpt:gpio name="io_sdr_DATA[15]" gpio_def="GPIOR_94" mode="inout" bus_name="io_sdr_DATA" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
<efxpt:input_config name="i_sdr_DATA[15]" name_ddio_lo="" conn_type="normal" is_register="true" clock_name="i_sdrclk" is_clock_inverted="false" pull_option="none" is_schmitt_trigger="false" ddio_type="none"/>
<efxpt:output_config name="o_sdr_DATA[15]" name_ddio_lo="" register_option="register" clock_name="i_sdrclk" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" drive_strength="3"/>
<efxpt:output_enable_config name="o_sdr_DATA_oe[15]" is_register="true" clock_name="i_sdrclk" is_clock_inverted="false"/>
</efxpt:gpio>
<efxpt:gpio name="io_sdr_DATA[1]" gpio_def="GPIOR_90" mode="inout" bus_name="io_sdr_DATA" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
<efxpt:input_config name="i_sdr_DATA[1]" name_ddio_lo="" conn_type="normal" is_register="true" clock_name="i_sdrclk" is_clock_inverted="false" pull_option="none" is_schmitt_trigger="false" ddio_type="none"/>
<efxpt:output_config name="o_sdr_DATA[1]" name_ddio_lo="" register_option="register" clock_name="i_sdrclk" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" drive_strength="3"/>
<efxpt:output_enable_config name="o_sdr_DATA_oe[1]" is_register="true" clock_name="i_sdrclk" is_clock_inverted="false"/>
</efxpt:gpio>
<efxpt:gpio name="io_sdr_DATA[2]" gpio_def="GPIOR_97" mode="inout" bus_name="io_sdr_DATA" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
<efxpt:input_config name="i_sdr_DATA[2]" name_ddio_lo="" conn_type="normal" is_register="true" clock_name="i_sdrclk" is_clock_inverted="false" pull_option="none" is_schmitt_trigger="false" ddio_type="none"/>
<efxpt:output_config name="o_sdr_DATA[2]" name_ddio_lo="" register_option="register" clock_name="i_sdrclk" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" drive_strength="3"/>
<efxpt:output_enable_config name="o_sdr_DATA_oe[2]" is_register="true" clock_name="i_sdrclk" is_clock_inverted="false"/>
</efxpt:gpio>
<efxpt:gpio name="io_sdr_DATA[3]" gpio_def="GPIOR_95" mode="inout" bus_name="io_sdr_DATA" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
<efxpt:input_config name="i_sdr_DATA[3]" name_ddio_lo="" conn_type="normal" is_register="true" clock_name="i_sdrclk" is_clock_inverted="false" pull_option="none" is_schmitt_trigger="false" ddio_type="none"/>
<efxpt:output_config name="o_sdr_DATA[3]" name_ddio_lo="" register_option="register" clock_name="i_sdrclk" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" drive_strength="3"/>
<efxpt:output_enable_config name="o_sdr_DATA_oe[3]" is_register="true" clock_name="i_sdrclk" is_clock_inverted="false"/>
</efxpt:gpio>
<efxpt:gpio name="io_sdr_DATA[4]" gpio_def="GPIOR_93" mode="inout" bus_name="io_sdr_DATA" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
<efxpt:input_config name="i_sdr_DATA[4]" name_ddio_lo="" conn_type="normal" is_register="true" clock_name="i_sdrclk" is_clock_inverted="false" pull_option="none" is_schmitt_trigger="false" ddio_type="none"/>
<efxpt:output_config name="o_sdr_DATA[4]" name_ddio_lo="" register_option="register" clock_name="i_sdrclk" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" drive_strength="3"/>
<efxpt:output_enable_config name="o_sdr_DATA_oe[4]" is_register="true" clock_name="i_sdrclk" is_clock_inverted="false"/>
</efxpt:gpio>
<efxpt:gpio name="io_sdr_DATA[5]" gpio_def="GPIOR_83" mode="inout" bus_name="io_sdr_DATA" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
<efxpt:input_config name="i_sdr_DATA[5]" name_ddio_lo="" conn_type="normal" is_register="true" clock_name="i_sdrclk" is_clock_inverted="false" pull_option="none" is_schmitt_trigger="false" ddio_type="none"/>
<efxpt:output_config name="o_sdr_DATA[5]" name_ddio_lo="" register_option="register" clock_name="i_sdrclk" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" drive_strength="3"/>
<efxpt:output_enable_config name="o_sdr_DATA_oe[5]" is_register="true" clock_name="i_sdrclk" is_clock_inverted="false"/>
</efxpt:gpio>
<efxpt:gpio name="io_sdr_DATA[6]" gpio_def="GPIOR_84" mode="inout" bus_name="io_sdr_DATA" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
<efxpt:input_config name="i_sdr_DATA[6]" name_ddio_lo="" conn_type="normal" is_register="true" clock_name="i_sdrclk" is_clock_inverted="false" pull_option="none" is_schmitt_trigger="false" ddio_type="none"/>
<efxpt:output_config name="o_sdr_DATA[6]" name_ddio_lo="" register_option="register" clock_name="i_sdrclk" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" drive_strength="3"/>
<efxpt:output_enable_config name="o_sdr_DATA_oe[6]" is_register="true" clock_name="i_sdrclk" is_clock_inverted="false"/>
</efxpt:gpio>
<efxpt:gpio name="io_sdr_DATA[7]" gpio_def="GPIOR_82" mode="inout" bus_name="io_sdr_DATA" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
<efxpt:input_config name="i_sdr_DATA[7]" name_ddio_lo="" conn_type="normal" is_register="true" clock_name="i_sdrclk" is_clock_inverted="false" pull_option="none" is_schmitt_trigger="false" ddio_type="none"/>
<efxpt:output_config name="o_sdr_DATA[7]" name_ddio_lo="" register_option="register" clock_name="i_sdrclk" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" drive_strength="3"/>
<efxpt:output_enable_config name="o_sdr_DATA_oe[7]" is_register="true" clock_name="i_sdrclk" is_clock_inverted="false"/>
</efxpt:gpio>
<efxpt:gpio name="io_sdr_DATA[8]" gpio_def="GPIOR_136" mode="inout" bus_name="io_sdr_DATA" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
<efxpt:input_config name="i_sdr_DATA[8]" name_ddio_lo="" conn_type="normal" is_register="true" clock_name="i_sdrclk" is_clock_inverted="false" pull_option="none" is_schmitt_trigger="false" ddio_type="none"/>
<efxpt:output_config name="o_sdr_DATA[8]" name_ddio_lo="" register_option="register" clock_name="i_sdrclk" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" drive_strength="3"/>
<efxpt:output_enable_config name="o_sdr_DATA_oe[8]" is_register="true" clock_name="i_sdrclk" is_clock_inverted="false"/>
</efxpt:gpio>
<efxpt:gpio name="io_sdr_DATA[9]" gpio_def="GPIOR_119" mode="inout" bus_name="io_sdr_DATA" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
<efxpt:input_config name="i_sdr_DATA[9]" name_ddio_lo="" conn_type="normal" is_register="true" clock_name="i_sdrclk" is_clock_inverted="false" pull_option="none" is_schmitt_trigger="false" ddio_type="none"/>
<efxpt:output_config name="o_sdr_DATA[9]" name_ddio_lo="" register_option="register" clock_name="i_sdrclk" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" drive_strength="3"/>
<efxpt:output_enable_config name="o_sdr_DATA_oe[9]" is_register="true" clock_name="i_sdrclk" is_clock_inverted="false"/>
</efxpt:gpio>
<efxpt:gpio name="leds[0]" gpio_def="GPIOR_104" mode="output" bus_name="leds" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
<efxpt:output_config name="leds[0]" name_ddio_lo="" register_option="none" clock_name="" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" drive_strength="3"/>
</efxpt:gpio>
@@ -154,6 +234,75 @@
<efxpt:gpio name="leds[7]" gpio_def="GPIOR_156" mode="output" bus_name="leds" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
<efxpt:output_config name="leds[7]" name_ddio_lo="" register_option="none" clock_name="" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" drive_strength="3"/>
</efxpt:gpio>
<efxpt:gpio name="o_sdr_ADDR[0]" gpio_def="GPIOR_85" mode="output" bus_name="o_sdr_ADDR" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
<efxpt:output_config name="o_sdr_ADDR[0]" name_ddio_lo="" register_option="register" clock_name="i_sdrclk" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" drive_strength="3"/>
</efxpt:gpio>
<efxpt:gpio name="o_sdr_ADDR[10]" gpio_def="GPIOR_89" mode="output" bus_name="o_sdr_ADDR" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
<efxpt:output_config name="o_sdr_ADDR[10]" name_ddio_lo="" register_option="register" clock_name="i_sdrclk" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" drive_strength="3"/>
</efxpt:gpio>
<efxpt:gpio name="o_sdr_ADDR[11]" gpio_def="GPIOR_143" mode="output" bus_name="o_sdr_ADDR" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
<efxpt:output_config name="o_sdr_ADDR[11]" name_ddio_lo="" register_option="register" clock_name="i_sdrclk" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" drive_strength="3"/>
</efxpt:gpio>
<efxpt:gpio name="o_sdr_ADDR[12]" gpio_def="GPIOR_144" mode="output" bus_name="o_sdr_ADDR" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
<efxpt:output_config name="o_sdr_ADDR[12]" name_ddio_lo="" register_option="register" clock_name="i_sdrclk" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" drive_strength="3"/>
</efxpt:gpio>
<efxpt:gpio name="o_sdr_ADDR[1]" gpio_def="GPIOR_87" mode="output" bus_name="o_sdr_ADDR" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
<efxpt:output_config name="o_sdr_ADDR[1]" name_ddio_lo="" register_option="register" clock_name="i_sdrclk" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" drive_strength="3"/>
</efxpt:gpio>
<efxpt:gpio name="o_sdr_ADDR[2]" gpio_def="GPIOR_86" mode="output" bus_name="o_sdr_ADDR" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
<efxpt:output_config name="o_sdr_ADDR[2]" name_ddio_lo="" register_option="register" clock_name="i_sdrclk" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" drive_strength="3"/>
</efxpt:gpio>
<efxpt:gpio name="o_sdr_ADDR[3]" gpio_def="GPIOR_88" mode="output" bus_name="o_sdr_ADDR" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
<efxpt:output_config name="o_sdr_ADDR[3]" name_ddio_lo="" register_option="register" clock_name="i_sdrclk" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" drive_strength="3"/>
</efxpt:gpio>
<efxpt:gpio name="o_sdr_ADDR[4]" gpio_def="GPIOR_133" mode="output" bus_name="o_sdr_ADDR" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
<efxpt:output_config name="o_sdr_ADDR[4]" name_ddio_lo="" register_option="register" clock_name="i_sdrclk" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" drive_strength="3"/>
</efxpt:gpio>
<efxpt:gpio name="o_sdr_ADDR[5]" gpio_def="GPIOR_135" mode="output" bus_name="o_sdr_ADDR" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
<efxpt:output_config name="o_sdr_ADDR[5]" name_ddio_lo="" register_option="register" clock_name="i_sdrclk" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" drive_strength="3"/>
</efxpt:gpio>
<efxpt:gpio name="o_sdr_ADDR[6]" gpio_def="GPIOR_131" mode="output" bus_name="o_sdr_ADDR" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
<efxpt:output_config name="o_sdr_ADDR[6]" name_ddio_lo="" register_option="register" clock_name="i_sdrclk" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" drive_strength="3"/>
</efxpt:gpio>
<efxpt:gpio name="o_sdr_ADDR[7]" gpio_def="GPIOR_148" mode="output" bus_name="o_sdr_ADDR" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
<efxpt:output_config name="o_sdr_ADDR[7]" name_ddio_lo="" register_option="register" clock_name="i_sdrclk" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" drive_strength="3"/>
</efxpt:gpio>
<efxpt:gpio name="o_sdr_ADDR[8]" gpio_def="GPIOR_138" mode="output" bus_name="o_sdr_ADDR" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
<efxpt:output_config name="o_sdr_ADDR[8]" name_ddio_lo="" register_option="register" clock_name="i_sdrclk" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" drive_strength="3"/>
</efxpt:gpio>
<efxpt:gpio name="o_sdr_ADDR[9]" gpio_def="GPIOR_147" mode="output" bus_name="o_sdr_ADDR" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
<efxpt:output_config name="o_sdr_ADDR[9]" name_ddio_lo="" register_option="register" clock_name="i_sdrclk" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" drive_strength="3"/>
</efxpt:gpio>
<efxpt:gpio name="o_sdr_BA[0]" gpio_def="GPIOR_102" mode="output" bus_name="o_sdr_BA" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
<efxpt:output_config name="o_sdr_BA[0]" name_ddio_lo="" register_option="register" clock_name="i_sdrclk" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" drive_strength="3"/>
</efxpt:gpio>
<efxpt:gpio name="o_sdr_BA[1]" gpio_def="GPIOR_99" mode="output" bus_name="o_sdr_BA" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
<efxpt:output_config name="o_sdr_BA[1]" name_ddio_lo="" register_option="register" clock_name="i_sdrclk" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" drive_strength="3"/>
</efxpt:gpio>
<efxpt:gpio name="o_sdr_CK" gpio_def="GPIOR_146" mode="clkout" bus_name="" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
<efxpt:output_config name="" name_ddio_lo="" register_option="none" clock_name="i_sdrclk" is_clock_inverted="true" is_slew_rate="false" tied_option="none" ddio_type="none" drive_strength="3"/>
</efxpt:gpio>
<efxpt:gpio name="o_sdr_CKE" gpio_def="GPIOR_145" mode="output" bus_name="" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
<efxpt:output_config name="o_sdr_CKE" name_ddio_lo="" register_option="register" clock_name="i_sdrclk" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" drive_strength="3"/>
</efxpt:gpio>
<efxpt:gpio name="o_sdr_DQM[0]" gpio_def="GPIOR_80" mode="output" bus_name="o_sdr_DQM" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
<efxpt:output_config name="o_sdr_DQM[0]" name_ddio_lo="" register_option="register" clock_name="i_sdrclk" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" drive_strength="3"/>
</efxpt:gpio>
<efxpt:gpio name="o_sdr_DQM[1]" gpio_def="GPIOR_132" mode="output" bus_name="o_sdr_DQM" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
<efxpt:output_config name="o_sdr_DQM[1]" name_ddio_lo="" register_option="register" clock_name="i_sdrclk" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" drive_strength="3"/>
</efxpt:gpio>
<efxpt:gpio name="o_sdr_n_CAS" gpio_def="GPIOR_139" mode="output" bus_name="" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
<efxpt:output_config name="o_sdr_n_CAS" name_ddio_lo="" register_option="register" clock_name="i_sdrclk" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" drive_strength="2"/>
</efxpt:gpio>
<efxpt:gpio name="o_sdr_n_CS" gpio_def="GPIOR_103" mode="output" bus_name="" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
<efxpt:output_config name="o_sdr_n_CS" name_ddio_lo="" register_option="register" clock_name="i_sdrclk" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" drive_strength="3"/>
</efxpt:gpio>
<efxpt:gpio name="o_sdr_n_RAS" gpio_def="GPIOR_91" mode="output" bus_name="" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
<efxpt:output_config name="o_sdr_n_RAS" name_ddio_lo="" register_option="register" clock_name="i_sdrclk" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" drive_strength="3"/>
</efxpt:gpio>
<efxpt:gpio name="o_sdr_n_WE" gpio_def="GPIOR_141" mode="output" bus_name="" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
<efxpt:output_config name="o_sdr_n_WE" name_ddio_lo="" register_option="register" clock_name="i_sdrclk" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" drive_strength="3"/>
</efxpt:gpio>
<efxpt:gpio name="pll_in" gpio_def="GPIOR_157" mode="input" bus_name="" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
<efxpt:input_config name="pll_in" name_ddio_lo="" conn_type="pll_clkin" is_register="false" clock_name="" is_clock_inverted="false" pull_option="none" is_schmitt_trigger="false" ddio_type="none"/>
</efxpt:gpio>
@@ -161,12 +310,22 @@
<efxpt:bus name="cpu_data" mode="inout" msb="7" lsb="0"/>
<efxpt:bus name="cpu_addr" mode="input" msb="15" lsb="0"/>
<efxpt:bus name="leds" mode="output" msb="7" lsb="0"/>
<efxpt:bus name="io_sdr_DATA" mode="inout" msb="15" lsb="0"/>
<efxpt:bus name="o_sdr_ADDR" mode="output" msb="12" lsb="0"/>
<efxpt:bus name="o_sdr_BA" mode="output" msb="1" lsb="0"/>
<efxpt:bus name="o_sdr_DQM" mode="output" msb="1" lsb="0"/>
</efxpt:gpio_info>
<efxpt:pll_info>
<efxpt:pll name="pll_cpu_clk" pll_def="PLL_BR0" ref_clock_name="" ref_clock_freq="50.0000" multiplier="16" pre_divider="1" post_divider="8" reset_name="pll_cpu_reset" locked_name="pll_cpu_locked" is_ipfrz="false" is_bypass_lock="true">
<efxpt:output_clock name="clk_50" number="0" out_divider="2" adv_out_phase_shift="0"/>
<efxpt:output_clock name="clk_2" number="1" out_divider="50" adv_out_phase_shift="0"/>
<efxpt:adv_prop ref_clock_mode="external" ref_clock1_name="" ext_ref_clock_id="3" clksel_name="" feedback_clock_name="" feedback_mode="internal"/>
<efxpt:pll name="pll_cpu_clk" pll_def="PLL_TR1" ref_clock_name="i_sysclk" ref_clock_freq="100.0000" multiplier="16" pre_divider="2" post_divider="4" reset_name="pll_cpu_reset" locked_name="pll_cpu_locked" is_ipfrz="false" is_bypass_lock="true">
<efxpt:output_clock name="clk_50" number="0" out_divider="4" adv_out_phase_shift="0"/>
<efxpt:output_clock name="clk_2" number="1" out_divider="100" adv_out_phase_shift="0"/>
<efxpt:adv_prop ref_clock_mode="core" ref_clock1_name="" ext_ref_clock_id="2" clksel_name="" feedback_clock_name="" feedback_mode="internal"/>
</efxpt:pll>
<efxpt:pll name="pll_sdram_clk" pll_def="PLL_BR0" ref_clock_name="" ref_clock_freq="50.0000" multiplier="8" pre_divider="4" post_divider="2" reset_name="o_pll_reset" locked_name="i_pll_locked" is_ipfrz="false" is_bypass_lock="true">
<efxpt:output_clock name="i_sdrclk" number="0" out_divider="2" adv_out_phase_shift="0"/>
<efxpt:output_clock name="i_tACclk" number="1" out_divider="2" adv_out_phase_shift="0"/>
<efxpt:output_clock name="i_sysclk" number="2" out_divider="4" adv_out_phase_shift="0"/>
<efxpt:adv_prop ref_clock_mode="external" ref_clock1_name="" ext_ref_clock_id="3" clksel_name="" feedback_clock_name="i_sysclk" feedback_mode="core"/>
</efxpt:pll>
</efxpt:pll_info>
<efxpt:lvds_info/>

241
hw/efinix_fpga/super6502.pt.sdc
View File

@@ -1,9 +1,9 @@
# Efinity Interface Designer SDC
# Version: 2021.2.323.4.6
# Date: 2022-11-01 18:17
# Version: 2022.1.226
# Date: 2022-12-21 23:10
# Copyright (C) 2017 - 2021 Efinix Inc. All rights reserved.
# Copyright (C) 2017 - 2022 Efinix Inc. All rights reserved.
# Device: T20F256
# Project: super6502
@@ -11,49 +11,56 @@
# PLL Constraints
#################
create_clock -period 20.00 clk_50
create_clock -period 500.00 clk_2
create_clock -period 5.0000 i_sdrclk
create_clock -period 5.0000 i_tACclk
create_clock -period 10.0000 i_sysclk
create_clock -period 20.0000 clk_50
create_clock -period 500.0000 clk_2
# GPIO Constraints
####################
# set_input_delay -clock <CLOCK> -max <MAX CALCULATION> [get_ports {button_reset}]
# set_input_delay -clock <CLOCK> -min <MIN CALCULATION> [get_ports {button_reset}]
# set_input_delay -clock <CLOCK> -max <MAX CALCULATION> [get_ports {cpu_addr[0]}]
# set_input_delay -clock <CLOCK> -min <MIN CALCULATION> [get_ports {cpu_addr[0]}]
# set_input_delay -clock <CLOCK> -max <MAX CALCULATION> [get_ports {cpu_addr[1]}]
# set_input_delay -clock <CLOCK> -min <MIN CALCULATION> [get_ports {cpu_addr[1]}]
# set_input_delay -clock <CLOCK> -max <MAX CALCULATION> [get_ports {cpu_addr[2]}]
# set_input_delay -clock <CLOCK> -min <MIN CALCULATION> [get_ports {cpu_addr[2]}]
# set_input_delay -clock <CLOCK> -max <MAX CALCULATION> [get_ports {cpu_addr[3]}]
# set_input_delay -clock <CLOCK> -min <MIN CALCULATION> [get_ports {cpu_addr[3]}]
# set_input_delay -clock <CLOCK> -max <MAX CALCULATION> [get_ports {cpu_addr[4]}]
# set_input_delay -clock <CLOCK> -min <MIN CALCULATION> [get_ports {cpu_addr[4]}]
# set_input_delay -clock <CLOCK> -max <MAX CALCULATION> [get_ports {cpu_addr[5]}]
# set_input_delay -clock <CLOCK> -min <MIN CALCULATION> [get_ports {cpu_addr[5]}]
# set_input_delay -clock <CLOCK> -max <MAX CALCULATION> [get_ports {cpu_addr[6]}]
# set_input_delay -clock <CLOCK> -min <MIN CALCULATION> [get_ports {cpu_addr[6]}]
# set_input_delay -clock <CLOCK> -max <MAX CALCULATION> [get_ports {cpu_addr[7]}]
# set_input_delay -clock <CLOCK> -min <MIN CALCULATION> [get_ports {cpu_addr[7]}]
# set_input_delay -clock <CLOCK> -max <MAX CALCULATION> [get_ports {cpu_addr[8]}]
# set_input_delay -clock <CLOCK> -min <MIN CALCULATION> [get_ports {cpu_addr[8]}]
# set_input_delay -clock <CLOCK> -max <MAX CALCULATION> [get_ports {cpu_addr[9]}]
# set_input_delay -clock <CLOCK> -min <MIN CALCULATION> [get_ports {cpu_addr[9]}]
# set_input_delay -clock <CLOCK> -max <MAX CALCULATION> [get_ports {cpu_addr[10]}]
# set_input_delay -clock <CLOCK> -min <MIN CALCULATION> [get_ports {cpu_addr[10]}]
# set_input_delay -clock <CLOCK> -max <MAX CALCULATION> [get_ports {cpu_addr[11]}]
# set_input_delay -clock <CLOCK> -min <MIN CALCULATION> [get_ports {cpu_addr[11]}]
# set_input_delay -clock <CLOCK> -max <MAX CALCULATION> [get_ports {cpu_addr[12]}]
# set_input_delay -clock <CLOCK> -min <MIN CALCULATION> [get_ports {cpu_addr[12]}]
# set_input_delay -clock <CLOCK> -max <MAX CALCULATION> [get_ports {cpu_addr[13]}]
# set_input_delay -clock <CLOCK> -min <MIN CALCULATION> [get_ports {cpu_addr[13]}]
# set_input_delay -clock <CLOCK> -max <MAX CALCULATION> [get_ports {cpu_addr[14]}]
# set_input_delay -clock <CLOCK> -min <MIN CALCULATION> [get_ports {cpu_addr[14]}]
# set_input_delay -clock <CLOCK> -max <MAX CALCULATION> [get_ports {cpu_addr[15]}]
# set_input_delay -clock <CLOCK> -min <MIN CALCULATION> [get_ports {cpu_addr[15]}]
# set_input_delay -clock <CLOCK> -max <MAX CALCULATION> [get_ports {cpu_rwb}]
# set_input_delay -clock <CLOCK> -min <MIN CALCULATION> [get_ports {cpu_rwb}]
# set_input_delay -clock <CLOCK> -max <MAX CALCULATION> [get_ports {cpu_sync}]
# set_input_delay -clock <CLOCK> -min <MIN CALCULATION> [get_ports {cpu_sync}]
# set_input_delay -clock <CLOCK> -max <MAX CALCULATION> [get_ports {pll_in}]
# set_input_delay -clock <CLOCK> -min <MIN CALCULATION> [get_ports {pll_in}]
# set_output_delay -clock <CLOCK> -max <MAX CALCULATION> [get_ports {cpu_addr[0]}]
# set_output_delay -clock <CLOCK> -min <MIN CALCULATION> [get_ports {cpu_addr[0]}]
# set_output_delay -clock <CLOCK> -max <MAX CALCULATION> [get_ports {cpu_addr[1]}]
# set_output_delay -clock <CLOCK> -min <MIN CALCULATION> [get_ports {cpu_addr[1]}]
# set_output_delay -clock <CLOCK> -max <MAX CALCULATION> [get_ports {cpu_addr[2]}]
# set_output_delay -clock <CLOCK> -min <MIN CALCULATION> [get_ports {cpu_addr[2]}]
# set_output_delay -clock <CLOCK> -max <MAX CALCULATION> [get_ports {cpu_addr[3]}]
# set_output_delay -clock <CLOCK> -min <MIN CALCULATION> [get_ports {cpu_addr[3]}]
# set_output_delay -clock <CLOCK> -max <MAX CALCULATION> [get_ports {cpu_addr[4]}]
# set_output_delay -clock <CLOCK> -min <MIN CALCULATION> [get_ports {cpu_addr[4]}]
# set_output_delay -clock <CLOCK> -max <MAX CALCULATION> [get_ports {cpu_addr[5]}]
# set_output_delay -clock <CLOCK> -min <MIN CALCULATION> [get_ports {cpu_addr[5]}]
# set_output_delay -clock <CLOCK> -max <MAX CALCULATION> [get_ports {cpu_addr[6]}]
# set_output_delay -clock <CLOCK> -min <MIN CALCULATION> [get_ports {cpu_addr[6]}]
# set_output_delay -clock <CLOCK> -max <MAX CALCULATION> [get_ports {cpu_addr[7]}]
# set_output_delay -clock <CLOCK> -min <MIN CALCULATION> [get_ports {cpu_addr[7]}]
# set_output_delay -clock <CLOCK> -max <MAX CALCULATION> [get_ports {cpu_addr[8]}]
# set_output_delay -clock <CLOCK> -min <MIN CALCULATION> [get_ports {cpu_addr[8]}]
# set_output_delay -clock <CLOCK> -max <MAX CALCULATION> [get_ports {cpu_addr[9]}]
# set_output_delay -clock <CLOCK> -min <MIN CALCULATION> [get_ports {cpu_addr[9]}]
# set_output_delay -clock <CLOCK> -max <MAX CALCULATION> [get_ports {cpu_addr[10]}]
# set_output_delay -clock <CLOCK> -min <MIN CALCULATION> [get_ports {cpu_addr[10]}]
# set_output_delay -clock <CLOCK> -max <MAX CALCULATION> [get_ports {cpu_addr[11]}]
# set_output_delay -clock <CLOCK> -min <MIN CALCULATION> [get_ports {cpu_addr[11]}]
# set_output_delay -clock <CLOCK> -max <MAX CALCULATION> [get_ports {cpu_addr[12]}]
# set_output_delay -clock <CLOCK> -min <MIN CALCULATION> [get_ports {cpu_addr[12]}]
# set_output_delay -clock <CLOCK> -max <MAX CALCULATION> [get_ports {cpu_addr[13]}]
# set_output_delay -clock <CLOCK> -min <MIN CALCULATION> [get_ports {cpu_addr[13]}]
# set_output_delay -clock <CLOCK> -max <MAX CALCULATION> [get_ports {cpu_addr[14]}]
# set_output_delay -clock <CLOCK> -min <MIN CALCULATION> [get_ports {cpu_addr[14]}]
# set_output_delay -clock <CLOCK> -max <MAX CALCULATION> [get_ports {cpu_addr[15]}]
# set_output_delay -clock <CLOCK> -min <MIN CALCULATION> [get_ports {cpu_addr[15]}]
# set_output_delay -clock <CLOCK> -max <MAX CALCULATION> [get_ports {cpu_phi2}]
# set_output_delay -clock <CLOCK> -min <MIN CALCULATION> [get_ports {cpu_phi2}]
# set_output_delay -clock <CLOCK> -max <MAX CALCULATION> [get_ports {cpu_irqb}]
# set_output_delay -clock <CLOCK> -min <MIN CALCULATION> [get_ports {cpu_irqb}]
# set_output_delay -clock <CLOCK> -max <MAX CALCULATION> [get_ports {cpu_nmib}]
@@ -62,8 +69,68 @@ create_clock -period 500.00 clk_2
# set_output_delay -clock <CLOCK> -min <MIN CALCULATION> [get_ports {cpu_rdy}]
# set_output_delay -clock <CLOCK> -max <MAX CALCULATION> [get_ports {cpu_resb}]
# set_output_delay -clock <CLOCK> -min <MIN CALCULATION> [get_ports {cpu_resb}]
# set_output_delay -clock <CLOCK> -max <MAX CALCULATION> [get_ports {cpu_rwb}]
# set_output_delay -clock <CLOCK> -min <MIN CALCULATION> [get_ports {cpu_rwb}]
# set_output_delay -clock <CLOCK> -max <MAX CALCULATION> [get_ports {leds[0]}]
# set_output_delay -clock <CLOCK> -min <MIN CALCULATION> [get_ports {leds[0]}]
# set_output_delay -clock <CLOCK> -max <MAX CALCULATION> [get_ports {leds[1]}]
# set_output_delay -clock <CLOCK> -min <MIN CALCULATION> [get_ports {leds[1]}]
# set_output_delay -clock <CLOCK> -max <MAX CALCULATION> [get_ports {leds[2]}]
# set_output_delay -clock <CLOCK> -min <MIN CALCULATION> [get_ports {leds[2]}]
# set_output_delay -clock <CLOCK> -max <MAX CALCULATION> [get_ports {leds[3]}]
# set_output_delay -clock <CLOCK> -min <MIN CALCULATION> [get_ports {leds[3]}]
# set_output_delay -clock <CLOCK> -max <MAX CALCULATION> [get_ports {leds[4]}]
# set_output_delay -clock <CLOCK> -min <MIN CALCULATION> [get_ports {leds[4]}]
# set_output_delay -clock <CLOCK> -max <MAX CALCULATION> [get_ports {leds[5]}]
# set_output_delay -clock <CLOCK> -min <MIN CALCULATION> [get_ports {leds[5]}]
# set_output_delay -clock <CLOCK> -max <MAX CALCULATION> [get_ports {leds[6]}]
# set_output_delay -clock <CLOCK> -min <MIN CALCULATION> [get_ports {leds[6]}]
# set_output_delay -clock <CLOCK> -max <MAX CALCULATION> [get_ports {leds[7]}]
# set_output_delay -clock <CLOCK> -min <MIN CALCULATION> [get_ports {leds[7]}]
set_output_delay -clock i_sdrclk -max -3.500 [get_ports {o_sdr_ADDR[0]}]
set_output_delay -clock i_sdrclk -min -2.139 [get_ports {o_sdr_ADDR[0]}]
set_output_delay -clock i_sdrclk -max -3.500 [get_ports {o_sdr_ADDR[1]}]
set_output_delay -clock i_sdrclk -min -2.139 [get_ports {o_sdr_ADDR[1]}]
set_output_delay -clock i_sdrclk -max -3.500 [get_ports {o_sdr_ADDR[2]}]
set_output_delay -clock i_sdrclk -min -2.139 [get_ports {o_sdr_ADDR[2]}]
set_output_delay -clock i_sdrclk -max -3.500 [get_ports {o_sdr_ADDR[3]}]
set_output_delay -clock i_sdrclk -min -2.139 [get_ports {o_sdr_ADDR[3]}]
set_output_delay -clock i_sdrclk -max -3.500 [get_ports {o_sdr_ADDR[4]}]
set_output_delay -clock i_sdrclk -min -2.139 [get_ports {o_sdr_ADDR[4]}]
set_output_delay -clock i_sdrclk -max -3.500 [get_ports {o_sdr_ADDR[5]}]
set_output_delay -clock i_sdrclk -min -2.139 [get_ports {o_sdr_ADDR[5]}]
set_output_delay -clock i_sdrclk -max -3.500 [get_ports {o_sdr_ADDR[6]}]
set_output_delay -clock i_sdrclk -min -2.139 [get_ports {o_sdr_ADDR[6]}]
set_output_delay -clock i_sdrclk -max -3.500 [get_ports {o_sdr_ADDR[7]}]
set_output_delay -clock i_sdrclk -min -2.139 [get_ports {o_sdr_ADDR[7]}]
set_output_delay -clock i_sdrclk -max -3.500 [get_ports {o_sdr_ADDR[8]}]
set_output_delay -clock i_sdrclk -min -2.139 [get_ports {o_sdr_ADDR[8]}]
set_output_delay -clock i_sdrclk -max -3.500 [get_ports {o_sdr_ADDR[9]}]
set_output_delay -clock i_sdrclk -min -2.139 [get_ports {o_sdr_ADDR[9]}]
set_output_delay -clock i_sdrclk -max -3.500 [get_ports {o_sdr_ADDR[10]}]
set_output_delay -clock i_sdrclk -min -2.139 [get_ports {o_sdr_ADDR[10]}]
set_output_delay -clock i_sdrclk -max -3.500 [get_ports {o_sdr_ADDR[11]}]
set_output_delay -clock i_sdrclk -min -2.139 [get_ports {o_sdr_ADDR[11]}]
set_output_delay -clock i_sdrclk -max -3.500 [get_ports {o_sdr_ADDR[12]}]
set_output_delay -clock i_sdrclk -min -2.139 [get_ports {o_sdr_ADDR[12]}]
set_output_delay -clock i_sdrclk -max -3.500 [get_ports {o_sdr_BA[0]}]
set_output_delay -clock i_sdrclk -min -2.139 [get_ports {o_sdr_BA[0]}]
set_output_delay -clock i_sdrclk -max -3.500 [get_ports {o_sdr_BA[1]}]
set_output_delay -clock i_sdrclk -min -2.139 [get_ports {o_sdr_BA[1]}]
set_output_delay -clock i_sdrclk -max -3.500 [get_ports {o_sdr_CK}]
set_output_delay -clock i_sdrclk -min -2.139 [get_ports {o_sdr_CK}]
set_output_delay -clock i_sdrclk -max -3.500 [get_ports {o_sdr_CKE}]
set_output_delay -clock i_sdrclk -min -2.139 [get_ports {o_sdr_CKE}]
set_output_delay -clock i_sdrclk -max -3.500 [get_ports {o_sdr_DQM[0]}]
set_output_delay -clock i_sdrclk -min -2.139 [get_ports {o_sdr_DQM[0]}]
set_output_delay -clock i_sdrclk -max -3.500 [get_ports {o_sdr_DQM[1]}]
set_output_delay -clock i_sdrclk -min -2.139 [get_ports {o_sdr_DQM[1]}]
set_output_delay -clock i_sdrclk -max -3.500 [get_ports {o_sdr_n_CAS}]
set_output_delay -clock i_sdrclk -min -2.139 [get_ports {o_sdr_n_CAS}]
set_output_delay -clock i_sdrclk -max -3.500 [get_ports {o_sdr_n_CS}]
set_output_delay -clock i_sdrclk -min -2.139 [get_ports {o_sdr_n_CS}]
set_output_delay -clock i_sdrclk -max -3.500 [get_ports {o_sdr_n_RAS}]
set_output_delay -clock i_sdrclk -min -2.139 [get_ports {o_sdr_n_RAS}]
set_output_delay -clock i_sdrclk -max -3.500 [get_ports {o_sdr_n_WE}]
set_output_delay -clock i_sdrclk -min -2.139 [get_ports {o_sdr_n_WE}]
# set_input_delay -clock <CLOCK> -max <MAX CALCULATION> [get_ports {cpu_data_in[0]}]
# set_input_delay -clock <CLOCK> -min <MIN CALCULATION> [get_ports {cpu_data_in[0]}]
# set_output_delay -clock <CLOCK> -max <MAX CALCULATION> [get_ports {cpu_data_out[0]}]
@@ -112,3 +179,99 @@ create_clock -period 500.00 clk_2
# set_output_delay -clock <CLOCK> -min <MIN CALCULATION> [get_ports {cpu_data_out[7]}]
# set_output_delay -clock <CLOCK> -max <MAX CALCULATION> [get_ports {cpu_data_oe[7]}]
# set_output_delay -clock <CLOCK> -min <MIN CALCULATION> [get_ports {cpu_data_oe[7]}]
set_input_delay -clock i_sdrclk -max 4.968 [get_ports {i_sdr_DATA[0]}]
set_input_delay -clock i_sdrclk -min 2.484 [get_ports {i_sdr_DATA[0]}]
set_output_delay -clock i_sdrclk -max -3.500 [get_ports {o_sdr_DATA[0]}]
set_output_delay -clock i_sdrclk -min -2.139 [get_ports {o_sdr_DATA[0]}]
set_output_delay -clock i_sdrclk -max -3.507 [get_ports {o_sdr_DATA_oe[0]}]
set_output_delay -clock i_sdrclk -min -2.143 [get_ports {o_sdr_DATA_oe[0]}]
set_input_delay -clock i_sdrclk -max 4.968 [get_ports {i_sdr_DATA[1]}]
set_input_delay -clock i_sdrclk -min 2.484 [get_ports {i_sdr_DATA[1]}]
set_output_delay -clock i_sdrclk -max -3.500 [get_ports {o_sdr_DATA[1]}]
set_output_delay -clock i_sdrclk -min -2.139 [get_ports {o_sdr_DATA[1]}]
set_output_delay -clock i_sdrclk -max -3.507 [get_ports {o_sdr_DATA_oe[1]}]
set_output_delay -clock i_sdrclk -min -2.143 [get_ports {o_sdr_DATA_oe[1]}]
set_input_delay -clock i_sdrclk -max 4.968 [get_ports {i_sdr_DATA[2]}]
set_input_delay -clock i_sdrclk -min 2.484 [get_ports {i_sdr_DATA[2]}]
set_output_delay -clock i_sdrclk -max -3.500 [get_ports {o_sdr_DATA[2]}]
set_output_delay -clock i_sdrclk -min -2.139 [get_ports {o_sdr_DATA[2]}]
set_output_delay -clock i_sdrclk -max -3.507 [get_ports {o_sdr_DATA_oe[2]}]
set_output_delay -clock i_sdrclk -min -2.143 [get_ports {o_sdr_DATA_oe[2]}]
set_input_delay -clock i_sdrclk -max 4.968 [get_ports {i_sdr_DATA[3]}]
set_input_delay -clock i_sdrclk -min 2.484 [get_ports {i_sdr_DATA[3]}]
set_output_delay -clock i_sdrclk -max -3.500 [get_ports {o_sdr_DATA[3]}]
set_output_delay -clock i_sdrclk -min -2.139 [get_ports {o_sdr_DATA[3]}]
set_output_delay -clock i_sdrclk -max -3.507 [get_ports {o_sdr_DATA_oe[3]}]
set_output_delay -clock i_sdrclk -min -2.143 [get_ports {o_sdr_DATA_oe[3]}]
set_input_delay -clock i_sdrclk -max 4.968 [get_ports {i_sdr_DATA[4]}]
set_input_delay -clock i_sdrclk -min 2.484 [get_ports {i_sdr_DATA[4]}]
set_output_delay -clock i_sdrclk -max -3.500 [get_ports {o_sdr_DATA[4]}]
set_output_delay -clock i_sdrclk -min -2.139 [get_ports {o_sdr_DATA[4]}]
set_output_delay -clock i_sdrclk -max -3.507 [get_ports {o_sdr_DATA_oe[4]}]
set_output_delay -clock i_sdrclk -min -2.143 [get_ports {o_sdr_DATA_oe[4]}]
set_input_delay -clock i_sdrclk -max 5.768 [get_ports {i_sdr_DATA[5]}]
set_input_delay -clock i_sdrclk -min 2.884 [get_ports {i_sdr_DATA[5]}]
set_output_delay -clock i_sdrclk -max -3.500 [get_ports {o_sdr_DATA[5]}]
set_output_delay -clock i_sdrclk -min -2.139 [get_ports {o_sdr_DATA[5]}]
set_output_delay -clock i_sdrclk -max -3.507 [get_ports {o_sdr_DATA_oe[5]}]
set_output_delay -clock i_sdrclk -min -2.143 [get_ports {o_sdr_DATA_oe[5]}]
set_input_delay -clock i_sdrclk -max 5.568 [get_ports {i_sdr_DATA[6]}]
set_input_delay -clock i_sdrclk -min 2.784 [get_ports {i_sdr_DATA[6]}]
set_output_delay -clock i_sdrclk -max -3.500 [get_ports {o_sdr_DATA[6]}]
set_output_delay -clock i_sdrclk -min -2.139 [get_ports {o_sdr_DATA[6]}]
set_output_delay -clock i_sdrclk -max -3.507 [get_ports {o_sdr_DATA_oe[6]}]
set_output_delay -clock i_sdrclk -min -2.143 [get_ports {o_sdr_DATA_oe[6]}]
set_input_delay -clock i_sdrclk -max 5.768 [get_ports {i_sdr_DATA[7]}]
set_input_delay -clock i_sdrclk -min 2.884 [get_ports {i_sdr_DATA[7]}]
set_output_delay -clock i_sdrclk -max -3.500 [get_ports {o_sdr_DATA[7]}]
set_output_delay -clock i_sdrclk -min -2.139 [get_ports {o_sdr_DATA[7]}]
set_output_delay -clock i_sdrclk -max -3.507 [get_ports {o_sdr_DATA_oe[7]}]
set_output_delay -clock i_sdrclk -min -2.143 [get_ports {o_sdr_DATA_oe[7]}]
set_input_delay -clock i_sdrclk -max 4.968 [get_ports {i_sdr_DATA[8]}]
set_input_delay -clock i_sdrclk -min 2.484 [get_ports {i_sdr_DATA[8]}]
set_output_delay -clock i_sdrclk -max -3.500 [get_ports {o_sdr_DATA[8]}]
set_output_delay -clock i_sdrclk -min -2.139 [get_ports {o_sdr_DATA[8]}]
set_output_delay -clock i_sdrclk -max -3.507 [get_ports {o_sdr_DATA_oe[8]}]
set_output_delay -clock i_sdrclk -min -2.143 [get_ports {o_sdr_DATA_oe[8]}]
set_input_delay -clock i_sdrclk -max 4.968 [get_ports {i_sdr_DATA[9]}]
set_input_delay -clock i_sdrclk -min 2.484 [get_ports {i_sdr_DATA[9]}]
set_output_delay -clock i_sdrclk -max -3.500 [get_ports {o_sdr_DATA[9]}]
set_output_delay -clock i_sdrclk -min -2.139 [get_ports {o_sdr_DATA[9]}]
set_output_delay -clock i_sdrclk -max -3.507 [get_ports {o_sdr_DATA_oe[9]}]
set_output_delay -clock i_sdrclk -min -2.143 [get_ports {o_sdr_DATA_oe[9]}]
set_input_delay -clock i_sdrclk -max 4.968 [get_ports {i_sdr_DATA[10]}]
set_input_delay -clock i_sdrclk -min 2.484 [get_ports {i_sdr_DATA[10]}]
set_output_delay -clock i_sdrclk -max -3.500 [get_ports {o_sdr_DATA[10]}]
set_output_delay -clock i_sdrclk -min -2.139 [get_ports {o_sdr_DATA[10]}]
set_output_delay -clock i_sdrclk -max -3.507 [get_ports {o_sdr_DATA_oe[10]}]
set_output_delay -clock i_sdrclk -min -2.143 [get_ports {o_sdr_DATA_oe[10]}]
set_input_delay -clock i_sdrclk -max 4.968 [get_ports {i_sdr_DATA[11]}]
set_input_delay -clock i_sdrclk -min 2.484 [get_ports {i_sdr_DATA[11]}]
set_output_delay -clock i_sdrclk -max -3.500 [get_ports {o_sdr_DATA[11]}]
set_output_delay -clock i_sdrclk -min -2.139 [get_ports {o_sdr_DATA[11]}]
set_output_delay -clock i_sdrclk -max -3.507 [get_ports {o_sdr_DATA_oe[11]}]
set_output_delay -clock i_sdrclk -min -2.143 [get_ports {o_sdr_DATA_oe[11]}]
set_input_delay -clock i_sdrclk -max 4.968 [get_ports {i_sdr_DATA[12]}]
set_input_delay -clock i_sdrclk -min 2.484 [get_ports {i_sdr_DATA[12]}]
set_output_delay -clock i_sdrclk -max -3.500 [get_ports {o_sdr_DATA[12]}]
set_output_delay -clock i_sdrclk -min -2.139 [get_ports {o_sdr_DATA[12]}]
set_output_delay -clock i_sdrclk -max -3.507 [get_ports {o_sdr_DATA_oe[12]}]
set_output_delay -clock i_sdrclk -min -2.143 [get_ports {o_sdr_DATA_oe[12]}]
set_input_delay -clock i_sdrclk -max 4.968 [get_ports {i_sdr_DATA[13]}]
set_input_delay -clock i_sdrclk -min 2.484 [get_ports {i_sdr_DATA[13]}]
set_output_delay -clock i_sdrclk -max -3.500 [get_ports {o_sdr_DATA[13]}]
set_output_delay -clock i_sdrclk -min -2.139 [get_ports {o_sdr_DATA[13]}]
set_output_delay -clock i_sdrclk -max -3.507 [get_ports {o_sdr_DATA_oe[13]}]
set_output_delay -clock i_sdrclk -min -2.143 [get_ports {o_sdr_DATA_oe[13]}]
set_input_delay -clock i_sdrclk -max 4.968 [get_ports {i_sdr_DATA[14]}]
set_input_delay -clock i_sdrclk -min 2.484 [get_ports {i_sdr_DATA[14]}]
set_output_delay -clock i_sdrclk -max -3.500 [get_ports {o_sdr_DATA[14]}]
set_output_delay -clock i_sdrclk -min -2.139 [get_ports {o_sdr_DATA[14]}]
set_output_delay -clock i_sdrclk -max -3.507 [get_ports {o_sdr_DATA_oe[14]}]
set_output_delay -clock i_sdrclk -min -2.143 [get_ports {o_sdr_DATA_oe[14]}]
set_input_delay -clock i_sdrclk -max 4.968 [get_ports {i_sdr_DATA[15]}]
set_input_delay -clock i_sdrclk -min 2.484 [get_ports {i_sdr_DATA[15]}]
set_output_delay -clock i_sdrclk -max -3.500 [get_ports {o_sdr_DATA[15]}]
set_output_delay -clock i_sdrclk -min -2.139 [get_ports {o_sdr_DATA[15]}]
set_output_delay -clock i_sdrclk -max -3.507 [get_ports {o_sdr_DATA_oe[15]}]
set_output_delay -clock i_sdrclk -min -2.143 [get_ports {o_sdr_DATA_oe[15]}]

62
hw/efinix_fpga/super6502.sv
View File

@@ -1,5 +1,9 @@
module super6502
(
input logic i_sysclk, // Controller Clock (100MHz)
input logic i_sdrclk, // t_su and t_wd clock (200MHz)
input logic i_tACclk, // t_ac clock (200MHz)
input [7:0] cpu_data_in,
input cpu_sync,
input cpu_rwb,
@@ -18,10 +22,25 @@ module super6502
output logic pll_cpu_reset,
output logic cpu_phi2,
output logic [7:0] leds
output logic [7:0] leds,
output logic o_pll_reset,
output logic o_sdr_CKE,
output logic o_sdr_n_CS,
output logic o_sdr_n_WE,
output logic o_sdr_n_RAS,
output logic o_sdr_n_CAS,
output logic [1:0] o_sdr_BA,
output logic [12:0] o_sdr_ADDR,
input logic [15:0] i_sdr_DATA,
output logic [15:0] o_sdr_DATA,
output logic [15:0] o_sdr_DATA_oe,
output logic [1:0] o_sdr_DQM
);
assign pll_cpu_reset = '1;
assign o_pll_reset = '1;
assign cpu_data_oe = {8{cpu_rwb}};
assign cpu_rdy = '1;
@@ -30,12 +49,14 @@ assign cpu_nmib = '1;
assign cpu_phi2 = clk_2;
logic w_sdr_init_done;
always @(posedge clk_2) begin
if (button_reset == '0) begin
cpu_resb <= '0;
end
else begin
if (cpu_resb == '0) begin
if (cpu_resb == '0 && w_sdr_init_done) begin
cpu_resb <= '1;
end
end
@@ -44,21 +65,26 @@ end
logic w_rom_cs;
logic w_leds_cs;
logic w_sdram_cs;
addr_decode u_addr_decode(
.i_addr(cpu_addr),
.o_rom_cs(w_rom_cs),
.o_leds_cs(w_leds_cs)
.o_leds_cs(w_leds_cs),
.o_sdram_cs(w_sdram_cs)
);
logic [7:0] w_rom_data_out;
logic [7:0] w_leds_data_out;
logic [7:0] w_sdram_data_out;
always_comb begin
if (w_rom_cs)
cpu_data_out = w_rom_data_out;
else if (w_leds_cs)
cpu_data_out = w_leds_data_out;
else if (w_sdram_cs)
cpu_data_out = w_sdram_data_out;
else
cpu_data_out = 'x;
end
@@ -84,4 +110,34 @@ leds u_leds(
.o_leds(leds)
);
sdram_adapter u_sdram_adapter(
.i_cpuclk(clk_2),
.i_arst(~button_reset),
.i_sysclk(i_sysclk),
.i_sdrclk(i_sdrclk),
.i_tACclk(i_tACclk),
.i_cs(w_sdram_cs),
.i_rwb(cpu_rwb),
.i_addr(cpu_addr),
.i_data(cpu_data_in),
.o_data(w_sdram_data_out),
.o_sdr_init_done(w_sdr_init_done),
.o_sdr_CKE(o_sdr_CKE),
.o_sdr_n_CS(o_sdr_n_CS),
.o_sdr_n_RAS(o_sdr_n_RAS),
.o_sdr_n_CAS(o_sdr_n_CAS),
.o_sdr_n_WE(o_sdr_n_WE),
.o_sdr_BA(o_sdr_BA),
.o_sdr_ADDR(o_sdr_ADDR),
.o_sdr_DATA(o_sdr_DATA),
.o_sdr_DATA_oe(o_sdr_DATA_oe),
.i_sdr_DATA(i_sdr_DATA),
.o_sdr_DQM(o_sdr_DQM)
);
endmodule

14
hw/efinix_fpga/super6502.xml
View File

@@ -1,12 +1,12 @@
<?xml version="1.0" encoding="UTF-8"?>
<efx:project name="super6502" description="" last_change_date="Tue December 20 2022 19:24:38" location="/home/byron/Projects/super6502/hw/efinix_fpga" sw_version="2022.1.226" last_run_state="pass" last_run_tool="efx_pgm" last_run_flow="bitstream" config_result_in_sync="true" design_ood="sync" place_ood="sync" route_ood="sync" xmlns:efx="http://www.efinixinc.com/enf_proj" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:schemaLocation="http://www.efinixinc.com/enf_proj enf_proj.xsd">
<efx:project name="super6502" description="" last_change_date="Thu December 22 2022 20:21:20" location="/home/byron/Projects/super6502/hw/efinix_fpga" sw_version="2022.1.226" last_run_state="pass" last_run_tool="efx_pgm" last_run_flow="bitstream" config_result_in_sync="true" design_ood="sync" place_ood="sync" route_ood="sync" xmlns:efx="http://www.efinixinc.com/enf_proj" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:schemaLocation="http://www.efinixinc.com/enf_proj enf_proj.xsd">
<efx:device_info>
<efx:family name="Trion"/>
<efx:device name="T20F256"/>
<efx:timing_model name="C4"/>
</efx:device_info>
<efx:design_info def_veri_version="sv_09" def_vhdl_version="vhdl_2008">
<efx:top_module name=""/>
<efx:top_module name="super6502"/>
<efx:design_file name="super6502.sv" version="default" library="default"/>
<efx:design_file name="ip/bram/bram_primitive.v" version="verilog_2k" library="default"/>
<efx:design_file name="ip/bram/bram_decompose.vh" version="verilog_2k" library="default"/>
@@ -15,6 +15,7 @@
<efx:design_file name="ip/bram/bram_wrapper_mwm.v" version="verilog_2k" library="default"/>
<efx:design_file name="leds.sv" version="default" library="default"/>
<efx:design_file name="addr_decode.sv" version="default" library="default"/>
<efx:design_file name="sdram_adapter.sv" version="default" library="default"/>
<efx:top_vhdl_arch name=""/>
</efx:design_info>
<efx:constraint_info>
@@ -23,7 +24,11 @@
</efx:constraint_info>
<efx:sim_info/>
<efx:misc_info/>
<efx:ip_info/>
<efx:ip_info>
<efx:ip instance_name="sdram_controller" path="ip/sdram_controller/settings.json">
<efx:ip_src_file name="sdram_controller.v"/>
</efx:ip>
</efx:ip_info>
<efx:synthesis tool_name="efx_map">
<efx:param name="work_dir" value="work_syn" value_type="e_string"/>
<efx:param name="write_efx_verilog" value="on" value_type="e_bool"/>
@@ -47,6 +52,7 @@
<efx:param name="allow-const-ram-index" value="0" value_type="e_option"/>
<efx:param name="hdl-compile-unit" value="1" value_type="e_option"/>
<efx:param name="create-onehot-fsms" value="0" value_type="e_option"/>
<efx:param name="include" value="ip/sdram_controller" value_type="e_string"/>
</efx:synthesis>
<efx:place_and_route tool_name="efx_pnr">
<efx:param name="work_dir" value="work_pnr" value_type="e_string"/>
@@ -79,7 +85,7 @@
</efx:bitstream_generation>
<efx:debugger>
<efx:param name="work_dir" value="work_dbg" value_type="e_string"/>
<efx:param name="auto_instantiation" value="off" value_type="e_bool"/>
<efx:param name="auto_instantiation" value="on" value_type="e_bool"/>
<efx:param name="profile" value="debug_profile.wizard.json" value_type="e_string"/>
</efx:debugger>
</efx:project>