Add write flag and reset logic for read flag

2023-01-12 14:04:44 -06:00
parent ab46236816
commit d5bccd46e3
1 changed files with 5 additions and 0 deletions
--- a/hw/efinix_fpga/uart_wrapper.sv
+++ b/hw/efinix_fpga/uart_wrapper.sv
@@ -54,7 +54,12 @@ always_ff @(posedge clk_50) begin
 end

 always_ff @(negedge clk) begin
+    status[1] <= tx_busy | tx_en;
+
    status[0] <= status[0] | rx_data_valid;
+    if (cs & ~addr & rwb) begin
+        status[0] <= 0;
+    end

    if (cs & ~rwb) begin
        case (addr)