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Add write flag and reset logic for read flag

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Byron Lathi
2023-01-12 14:04:44 -06:00
parent ab46236816
commit d5bccd46e3
1 changed files with 5 additions and 0 deletions
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5
hw/efinix_fpga/uart_wrapper.sv
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@@ -54,7 +54,12 @@ always_ff @(posedge clk_50) begin
end end
always_ff @(negedge clk) begin always_ff @(negedge clk) begin
status[1] <= tx_busy | tx_en;
status[0] <= status[0] | rx_data_valid; status[0] <= status[0] | rx_data_valid;
if (cs & ~addr & rwb) begin
status[0] <= 0;
end
if (cs & ~rwb) begin if (cs & ~rwb) begin
case (addr) case (addr)