Merge branch '49-verify-rtc' into 'master'

Resolve "Verify RTC"

Closes #49

See merge request bslathi19/super6502!45

.gitlab-ci.yml

@@ -146,4 +146,19 @@ interrupt_controller_code sim:
     - cd hw/efinix_fpga/simulation
     - make clean
     - TEST_PROGRAM_NAME=mapper_test make interrupt_controller_code_tb
-    - ./interrupt_controller_code_tb
+    - ./interrupt_controller_code_tb
+
+rtc_code sim:
+  tags:
+    - linux
+    - iverilog
+  stage: simulate
+  artifacts:
+    paths:
+      - hw/efinix_fpga/simulation/interrupt_controller_code.vcd
+  script:
+    - source init_env.sh
+    - cd hw/efinix_fpga/simulation
+    - make clean
+    - TEST_PROGRAM_NAME=rtc_test make rtc_code_tb
+    - ./rtc_code_tb

hw/efinix_fpga/simulation/Makefile

@@ -10,7 +10,7 @@ TEST_FOLDER?=$(REPO_TOP)/sw/test_code/$(TEST_PROGRAM_NAME)
 TEST_PROGRAM?=$(REPO_TOP)/sw/test_code/$(TEST_PROGRAM_NAME)/$(TEST_PROGRAM_NAME).hex
 
 STANDALONE_TB= interrupt_controller_tb mapper_tb rtc_tb
-CODE_TB= interrupt_controller_code_tb mapper_code_tb
+CODE_TB= interrupt_controller_code_tb mapper_code_tb rtc_code_tb
 
 #TODO implement something like sources.list
 

hw/efinix_fpga/simulation/tbs/interrupt_controller_code_tb.sv

@@ -21,11 +21,11 @@ always begin
 end
 
 initial begin
-    u_sim_top.u_dut.int_in = 0;
+    // u_sim_top.u_dut.w_int_in = 0;
     repeat (2400) @(posedge u_sim_top.r_clk_cpu);
     for (int i = 0; i < 256; i++) begin
         repeat (100) @(posedge u_sim_top.r_clk_cpu);
-        u_sim_top.u_dut.int_in = 1 << i;
+        force u_sim_top.u_dut.u_interrupt_controller.int_in = 1 << i;
         $display("Activiating interrupt %d", i);
     end
 end

hw/efinix_fpga/simulation/tbs/rtc_code_tb.sv

@@ -0,0 +1,49 @@
+`timescale 1ns/1ps
+
+module rtc_code_tb();
+
+sim_top u_sim_top();
+
+always begin
+    if (
+        u_sim_top.w_cpu_addr == 16'h0 &&
+        u_sim_top.w_cpu_we == '1
+    ) begin
+        if (u_sim_top.w_cpu_data_from_cpu == 8'h6d) begin
+            $display("Good finish!");
+            $finish();
+        end else begin
+            $display("Bad finish!");
+            $finish_and_return(-1);
+        end
+    end
+    # 1;
+end
+
+localparam increment = 3;
+
+logic [7:0] prev;
+initial prev = '0;
+
+always @(u_sim_top.w_cpu_addr) begin
+    if (
+        u_sim_top.w_cpu_addr == 16'h1 &&
+        u_sim_top.w_cpu_we == '1
+    ) begin
+        if (u_sim_top.w_cpu_data_from_cpu <= prev) begin
+            $display("Value didn't increment!");
+            $display("Bad finish!");
+            $finish_and_return(-1);
+        end
+        prev = u_sim_top.w_cpu_data_from_cpu;
+        $display("print1: %x", u_sim_top.w_cpu_data_from_cpu);
+    end
+end
+
+initial begin
+    repeat (5000) @(posedge u_sim_top.r_clk_cpu);
+    $display("Timed out");
+    $finish_and_return(-1);
+end
+
+endmodule

hw/efinix_fpga/src/super6502.sv

@@ -72,6 +72,8 @@ always @(posedge clk_cpu) begin
 end
 
 
+logic w_rtc_irq;
+
 logic w_mapper_cs;
 
 logic w_rom_cs;
@@ -83,6 +85,7 @@ logic w_divider_cs;
 logic w_uart_cs;
 logic w_spi_cs;
 logic w_irq_cs;
+logic w_rtc_cs;
 
 
 logic [7:0] w_rom_data_out;
@@ -93,6 +96,7 @@ logic [7:0] w_divider_data_out;
 logic [7:0] w_uart_data_out;
 logic [7:0] w_spi_data_out;
 logic [7:0] w_irq_data_out;
+logic [7:0] w_rtc_data_out;
 logic [7:0] w_sdram_data_out;
 
 logic [24:0] w_mapped_addr;
@@ -101,13 +105,14 @@ always_comb begin
     w_mapper_cs = cpu_addr >= 16'h200 && cpu_addr <= 16'h21f;
 
     w_rom_cs = w_mapped_addr >= 16'hf000 && w_mapped_addr <= 16'hffff;
+    w_rtc_cs = w_mapped_addr >= 16'heffe && w_mapped_addr <= 16'hefff;
     w_irq_cs = w_mapped_addr >= 16'heffc && w_mapped_addr <= 16'heffd;
     w_timer_cs = w_mapped_addr >= 16'heff8 && w_mapped_addr <= 16'heffb;
     w_multiplier_cs = w_mapped_addr >= 16'heff0 && w_mapped_addr <= 16'heff7;
     w_divider_cs = w_mapped_addr >= 16'hefe8 && w_mapped_addr <= 16'hefef;
     w_uart_cs = w_mapped_addr >= 16'hefe6 && w_mapped_addr <= 16'hefe7;
     w_spi_cs = w_mapped_addr >= 16'hefd8 && w_mapped_addr <= 16'hefdb;
-    w_leds_cs = w_mapped_addr == 16'hefff;
+    w_leds_cs = w_mapped_addr == 16'hefd7;
     
     w_sdram_cs = ~(
         w_rom_cs | 
@@ -117,7 +122,8 @@ always_comb begin
         w_uart_cs | 
         w_spi_cs |
         w_leds_cs |
-        w_irq_cs 
+        w_irq_cs |
+        w_rtc_cs
     );
 
 
@@ -139,6 +145,8 @@ always_comb begin
         cpu_data_out = w_spi_data_out;
     else if (w_irq_cs)
         cpu_data_out = w_irq_data_out;
+    else if (w_rtc_cs)
+        cpu_data_out = w_rtc_data_out;
     else if (w_sdram_cs)
         cpu_data_out = w_sdram_data_out;
     else
@@ -269,7 +277,9 @@ sdram_adapter u_sdram_adapter(
 
 logic w_irq;
 assign cpu_irqb = ~w_irq;
-logic [255:0] int_in;
+logic [255:0] w_int_in;
+
+assign w_int_in[255:1] = 0;
 
 interrupt_controller u_interrupt_controller(
     .clk(clk_cpu),
@@ -279,9 +289,21 @@ interrupt_controller u_interrupt_controller(
     .addr(w_mapped_addr[0]),
     .cs(w_irq_cs),
     .rwb(cpu_rwb),
-    .int_in(int_in),
+    .int_in(w_int_in),
     .int_out(w_irq)
 );
 
+rtc u_rtc(
+    .clk(clk_cpu),
+    .reset(~cpu_resb),
+    .rwb(cpu_rwb),
+    .cs(w_rtc_cs),
+    .addr(w_mapped_addr[0]),
+    .i_data(cpu_data_in),
+    .o_data(w_rtc_data_out),
+    .irq(w_rtc_irq)
+);
+
+assign w_int_in[0] = w_rtc_irq;
 
 endmodule

hw/efinix_fpga/super6502.xml

@@ -1,5 +1,5 @@
 <?xml version="1.0" encoding="UTF-8"?>
-<efx:project name="super6502" description="" last_change_date="Tue October 31 2023 23:42:24" location="/home/byron/Projects/super6502/hw/efinix_fpga" sw_version="2023.1.150" last_run_state="pass" last_run_tool="efx_pgm" last_run_flow="bitstream" config_result_in_sync="sync" design_ood="sync" place_ood="sync" route_ood="sync" xmlns:efx="http://www.efinixinc.com/enf_proj" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:schemaLocation="http://www.efinixinc.com/enf_proj enf_proj.xsd">
+<efx:project name="super6502" description="" last_change_date="Sun November 19 2023 15:04:04" location="/home/byron/Projects/super6502/hw/efinix_fpga" sw_version="2022.2.322" last_run_state="pass" last_run_tool="efx_pgm" last_run_flow="bitstream" config_result_in_sync="sync" design_ood="sync" place_ood="sync" route_ood="sync" xmlns:efx="http://www.efinixinc.com/enf_proj" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:schemaLocation="http://www.efinixinc.com/enf_proj enf_proj.xsd">
     <efx:device_info>
         <efx:family name="Trion"/>
         <efx:device name="T20F256"/>
@@ -21,6 +21,7 @@
         <efx:design_file name="src/spi_controller.sv" version="default" library="default"/>
         <efx:design_file name="src/mapper.sv" version="default" library="default"/>
         <efx:design_file name="src/byte_sel_register.sv" version="default" library="default"/>
+        <efx:design_file name="src/rtc.sv" version="default" library="default"/>
         <efx:top_vhdl_arch name=""/>
     </efx:design_info>
     <efx:constraint_info>

sw/test_code/irq_test/main.s

@@ -2,7 +2,7 @@
 
 .export _init, _nmi_int, _irq_int
 
-.import tmp1
+.importzp tmp1
 
 CMD = $effc
 DAT = $effd

sw/test_code/rtc_test/Makefile

@@ -0,0 +1,39 @@
+CC=../../cc65/bin/cl65
+LD=../../cc65/bin/cl65
+CFLAGS=-T -t none -I. --cpu "65C02"
+LDFLAGS=-C link.ld -m $(NAME).map
+
+NAME=rtc_test
+
+BIN=$(NAME).bin
+HEX=$(NAME).hex
+
+LISTS=lists
+
+SRCS=$(wildcard *.s) $(wildcard *.c)
+SRCS+=$(wildcard **/*.s) $(wildcard **/*.c)
+OBJS+=$(patsubst %.s,%.o,$(filter %s,$(SRCS)))
+OBJS+=$(patsubst %.c,%.o,$(filter %c,$(SRCS)))
+
+# Make sure the kernel linked to correct address, no relocation!
+all: $(HEX)
+
+$(HEX): $(BIN)
+	objcopy --input-target=binary --output-target=verilog $(BIN) $(HEX)
+
+$(BIN): $(OBJS)
+	$(CC) $(CFLAGS) $(LDFLAGS) $(OBJS) -o $@
+
+%.o: %.c $(LISTS)
+	$(CC) $(CFLAGS) -l $(LISTS)/$<.list -c $< -o $@
+
+%.o: %.s $(LISTS)
+	$(CC) $(CFLAGS) -l $(LISTS)/$<.list -c $< -o $@
+
+$(LISTS):
+	mkdir -p $(addprefix $(LISTS)/,$(sort $(dir $(SRCS))))
+
+.PHONY: clean
+clean:
+	rm -rf $(OBJS) $(BIN) $(HEX) $(LISTS) $(NAME).map
+

sw/test_code/rtc_test/link.ld

@@ -0,0 +1,35 @@
+MEMORY
+{
+  ZP:  start = $0,    size = $100,  type = rw, define = yes;
+  SDRAM: start = $9200, size = $4d00, type = rw, define = yes;
+  ROM: start = $F000, size = $1000, file = %O;
+}
+
+SEGMENTS {
+    ZEROPAGE: load = ZP,  type = zp,  define   = yes;
+    DATA:     load = ROM, type = rw,  define   = yes, run = SDRAM;
+    BSS:      load = SDRAM, type = bss, define   = yes;
+    HEAP:     load = SDRAM, type = bss, optional = yes;
+    STARTUP:  load = ROM, type = ro;
+    ONCE:     load = ROM, type = ro,  optional = yes;
+    CODE:     load = ROM, type = ro;
+    RODATA:   load = ROM, type = ro;
+    VECTORS:  load = ROM, type = ro,  start    = $FFFA;
+}
+
+FEATURES {
+    CONDES:    segment = STARTUP,
+               type    = constructor,
+               label   = __CONSTRUCTOR_TABLE__,
+               count   = __CONSTRUCTOR_COUNT__;
+    CONDES:    segment = STARTUP,
+               type    = destructor,
+               label   = __DESTRUCTOR_TABLE__,
+               count   = __DESTRUCTOR_COUNT__;
+}
+
+SYMBOLS {
+    # Define the stack size for the application
+    __STACKSIZE__:  value = $0200, type = weak;
+    __STACKSTART__: type = weak, value = $0800; # 2k stack
+}

sw/test_code/rtc_test/main.s

@@ -0,0 +1,79 @@
+.MACPACK generic
+
+.export _init, _nmi_int, _irq_int
+
+IRQ_CMD = $effc
+IRQ_DAT = $effd
+
+RTC_CMD = $effe
+RTC_DAT = $efff
+
+.zeropage
+finish: .res 1
+print: .res 1
+iters: .res 1
+
+.code
+
+_nmi_int:
+_irq_int:
+    lda #$30
+    sta RTC_CMD
+    lda RTC_DAT
+    sta print
+
+    lda iters
+    inc
+    cmp #$10
+    bge @end
+    sta iters
+    rti
+
+@end:
+    lda #$6d
+    sta finish
+
+_init:
+    ldx #$ff
+    txs
+
+    ; Enable irq0
+    lda #$20
+    sta IRQ_CMD
+    lda #$01
+    sta IRQ_DAT
+    ; edge type
+    lda #$40
+    sta IRQ_CMD
+    lda #$00
+    sta IRQ_DAT
+
+    ; Set increment
+    lda #$10
+    sta RTC_CMD
+    lda #$01
+    sta RTC_DAT
+
+    ; Set Threshold
+    lda #$00
+    sta RTC_CMD
+    lda #$07
+    sta RTC_DAT
+
+    ; Set IRQ Threshold
+    lda #$20
+    sta RTC_CMD
+    lda #$04
+    sta RTC_DAT
+
+    lda #$30
+    sta RTC_CMD
+    lda #$03
+    sta RTC_DAT
+
+    stz iters
+
+    cli
+
+wait:
+    bra wait

sw/test_code/rtc_test/vectors.s

@@ -0,0 +1,14 @@
+; ---------------------------------------------------------------------------
+; vectors.s
+; ---------------------------------------------------------------------------
+;
+; Defines the interrupt vector table.
+
+.import    _init
+.import    _nmi_int, _irq_int
+
+.segment  "VECTORS"
+
+.addr      _nmi_int    ; NMI vector
+.addr      _init       ; Reset vector
+.addr      _irq_int    ; IRQ/BRK vector