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Add platform generation to build stage

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Byron Lathi
2022-03-17 14:25:26 -05:00
parent 2d49fe22a7
commit ee97c4cbaa
1 changed files with 1 additions and 0 deletions
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.gitlab-ci.yml
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@@ -15,6 +15,7 @@ build-fpga:
image: bslathi19/modelsim_18.1:lite image: bslathi19/modelsim_18.1:lite
script: script:
- cd hw/fpga/ - cd hw/fpga/
- qsys-generate /builds/bslathi19/super6502/hw/fpga/sdram_platform.qsys --synthesis=VERILOG --output-directory=/builds/bslathi19/super6502/hw/fpga/sdram_platform --family="MAX 10" --part=10M50DAF484C7G
- quartus_map super6502 -c super6502 - quartus_map super6502 -c super6502
test_addr_decode: test_addr_decode: