switch to zipcpu sd sim

.gitmodules

@@ -7,9 +7,6 @@
 [submodule "hw/super6502_fpga/src/sim/sub/verilog-6502"]
 	path = hw/super6502_fpga/src/sim/sub/verilog-6502
 	url = ../verilog-6502.git
-[submodule "hw/super6502_fpga/src/sim/sub/verilog-sd-emulator"]
-	path = hw/super6502_fpga/src/sim/sub/verilog-sd-emulator
-	url = ../verilog-sd-emulator.git
 [submodule "hw/super6502_fpga/src/sub/wb2axip"]
 	path = hw/super6502_fpga/src/sub/wb2axip
 	url = ../wb2axip.git

hw/super6502_fpga/src/sim/hvl/sim_top.sv

@@ -162,13 +162,29 @@ super6502_fpga u_dut (
     .o_sd_clk               (o_sd_clk)
 );
 
-sd_card_emu u_sd_card_emu(
+wire w_sd_cmd;
-    .clk(o_sd_clk),
+wire w_sd_dat;
-    .rst(~button_resetn),
+
-    .i_cmd(o_sd_cmd),
+IOBUF cmd_buf (
-    .o_cmd(i_sd_cmd),
+    .T(o_sd_cmd_oe),
-    .i_dat(o_sd_dat),
+    .I(o_sd_cmd),
-    .o_dat(i_sd_dat)
+    .O(i_sd_cmd),
+    .IO(w_sd_cmd)
+);
+
+IOBUF dat_buf (
+    .T(o_sd_dat_oe),
+    .I(o_sd_dat),
+    .O(i_sd_dat),
+    .IO(w_sd_dat)
+);
+
+mdl_sdio #(
+    .LGMEMSZ(16)
+) u_sd_card_emu (
+    .sd_clk(o_sd_clk),
+    .sd_cmd(w_sd_cmd),
+    .sd_dat(w_sd_dat)
 );
 
 initial begin

hw/super6502_fpga/src/sim/sources.list

@@ -2,7 +2,8 @@ hvl/sim_top.sv
 sub/verilog-6502/ALU.v
 sub/verilog-6502/cpu_65c02.v
 sub/sim_sdram/generic_sdr.v
-sub/verilog-sd-emulator/src/sd_card_command.sv
+../sub/sd_controller_wrapper/sdspi/bench/verilog/mdl_sdio.v
-sub/verilog-sd-emulator/src/sd_card_emu.sv
+../sub/sd_controller_wrapper/sdspi/bench/verilog/mdl_sdcmd.v
-sub/verilog-sd-emulator/src/sd_card_state_controller.sv
+../sub/sd_controller_wrapper/sdspi/bench/verilog/mdl_sdrx.v
-sub/verilog-sd-emulator/src/sd_card_data.sv
+../sub/sd_controller_wrapper/sdspi/bench/verilog/mdl_sdtx.v
+../sub/sd_controller_wrapper/sdspi/bench/verilog/IOBUF.v