Byron Lathi
bc9b04853c
Merge branch '93-network-processor' into 'AXI-Rewrite'
...
Resolve "Network Processor"
Closes #93
See merge request bslathi19/super6502!74
2024-10-15 05:07:36 +00:00
Byron Lathi
105484b622
Merge branch '100-support-sending-fin' into '93-network-processor'
...
Resolve "Support Sending FIN"
See merge request bslathi19/super6502!80
2024-10-15 05:01:12 +00:00
Byron Lathi
8465b50712
makefile fixes, update efinity version
2024-10-14 21:50:06 -07:00
Byron Lathi
2307dd65e2
load efinity after init when building
2024-10-14 21:38:30 -07:00
Byron Lathi
411d091dc1
Increase seq when sending fins
2024-10-14 21:11:08 -07:00
Byron Lathi
16858bbb9d
Register signals explicitly
...
These were previously inferred latches, but now that they are not, we
need to register them explicitly, otherwise they will be 0
2024-10-13 20:21:53 -07:00
Byron Lathi
6bf7fee64b
Increase TCP count to 2
...
After removing all the inferred latches, we have enough space to have 2
TCP streams instead of just 1. Also we have way more timing slack.
Lesson learned, inferred latches are *really* bad and you should remove
them first before anything else.
2024-10-13 20:01:37 -07:00
Byron Lathi
5e8d91be53
Remove inferred latches
2024-10-13 19:50:02 -07:00
Byron Lathi
6265a8090c
Big update to try and pass timing. reduces tcp streams to 1
2024-10-13 18:43:12 -07:00
Byron Lathi
798fb6f20f
Get some fin support
2024-10-13 18:41:32 -07:00
Byron Lathi
982a8b52b6
Merge branch '97-calculate-checksum-for-tcp-data-also' into '93-network-processor'
...
Calculate checksum for tcp data also
See merge request bslathi19/super6502!77
2024-10-02 06:30:19 +00:00
Byron Lathi
7ebbef487b
Get a full tcp handshake, send data, and close cleanly
2024-10-01 21:38:17 -07:00
Byron Lathi
766fe72daf
add fin
2024-09-28 00:20:51 -07:00
Byron Lathi
00d982a538
Merge branch '96-send-tcp-data-over-m2s' into '93-network-processor'
...
Resolve "Send TCP data over M2S"
See merge request bslathi19/super6502!76
2024-09-23 06:52:23 +00:00
Byron Lathi
19e4344374
Make synthesis optional
2024-09-22 23:49:41 -07:00
Byron Lathi
8784de6fe3
Remove recv call
...
need to wait until checksum i presume
2024-09-22 22:30:22 -07:00
Byron Lathi
a774c3ac88
Try to recieve data
...
I think we need to actually do checksum for data
2024-09-22 21:57:50 -07:00
Byron Lathi
a78eae0278
Get tun0 test working locally
2024-09-22 20:26:30 -07:00
Byron Lathi
0ff3374185
Use scapy to send real packets
2024-09-21 21:07:35 -07:00
Byron Lathi
68fe3d1851
Add ntw sim to ci
2024-09-21 19:25:39 -07:00
Byron Lathi
404ad72b20
M2S a TCP
2024-09-21 19:17:42 -07:00
Byron Lathi
8cb7281116
Merge branch '95-calculate-tcp-checksum' into '93-network-processor'
...
Resolve "Calculate TCP Checksum"
See merge request bslathi19/super6502!75
2024-09-14 23:08:41 +00:00
Byron Lathi
40fe95ea0a
Add checksum calc to fpga sources
2024-09-14 15:26:22 -07:00
Byron Lathi
f742d9d89f
Add TCP calculator
2024-09-14 15:24:28 -07:00
Byron Lathi
fa80cab104
Length hacked a little less, hack window size
2024-09-13 08:23:00 -07:00
Byron Lathi
22fabf10f7
Hack length in
2024-09-13 08:06:36 -07:00
Byron Lathi
b815af3ff1
Make a pcapng file, not pcap
2024-09-13 07:41:17 -07:00
Byron Lathi
8455d5b56d
Handle ack in synack, write to pcap
2024-09-12 08:25:26 -07:00
Byron Lathi
812cb6447a
Add mii clocks to constraints
2024-09-09 23:18:56 -07:00
Byron Lathi
8be97b45ae
Move to 4 TCP units for synthesis
...
Otherwise it does not fit in the T20
2024-09-09 22:59:59 -07:00
Byron Lathi
4612acbc4a
Synthesis 1
2024-09-09 22:02:39 -07:00
Byron Lathi
e1f94f455c
Add basic acking to synacking
2024-09-08 18:15:43 -07:00
Byron Lathi
945889e542
Add up dest parser
2024-09-08 14:25:00 -07:00
Byron Lathi
ef20f1477d
Fix ip demux wrapper, send a tcp synack
2024-09-02 23:44:47 -07:00
Byron Lathi
0c2f36a2ff
Send ARP response, not request
2024-09-02 22:39:57 -07:00
Byron Lathi
87baa932f8
Clean up
2024-09-02 22:39:44 -07:00
Byron Lathi
efeca55a6c
Send basic header
2024-09-02 21:20:48 -07:00
Byron Lathi
3c5cabd2be
Update test, use scapy
2024-09-02 20:34:09 -07:00
Byron Lathi
30c7ed9c6a
Start work on tx ctrl
2024-09-02 20:33:50 -07:00
Byron Lathi
f4ab7b456d
Update so I can switch computers
2024-09-02 18:15:19 -07:00
Byron Lathi
1deceddcf6
update reg addr width, add fifo for m2s dma to write to
2024-09-02 14:48:57 -07:00
Byron Lathi
66855b050b
Move m2s dma into the tcp streams
2024-09-02 12:55:36 -07:00
Byron Lathi
247033ea2d
Uncomment module load
...
oops
2024-09-01 22:26:39 -07:00
Byron Lathi
73455e2be4
Remove sub from verilog-ethernet
2024-09-01 22:25:22 -07:00
Byron Lathi
dc90c00172
Mega commit to kick things off
2024-09-01 22:23:21 -07:00
Byron Lathi
8425d6a96e
Remove mux/demus from dma
2024-08-29 18:37:04 -07:00
Byron Lathi
e440aa7bdb
Change from ddr buffers to regular fifos
2024-08-29 18:33:52 -07:00
Byron Lathi
1bb613888f
Show errors in log file
2024-08-29 18:27:33 -07:00
Byron Lathi
6f8e976a08
Add basic m2s code
2024-08-20 19:01:37 -07:00
Byron Lathi
9030f4b71d
Separate ip streams
2024-08-20 18:57:24 -07:00
