Byron Lathi
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50b0860137
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Update testbench with more realistic timings
Updates the testbench to simulate writes with more correct timings.
Writes take two clock cycles since the cpu runs at half speed.
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2022-04-10 17:50:49 -05:00 |
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Byron Lathi
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31a4656cac
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Reduce sd_controller addr width from 4 to 3
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2022-04-09 17:31:25 -05:00 |
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Byron Lathi
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38566f7b4a
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add testbench for SD command tx
Sends a few commands which we know the proper checksum for and makes
sure that the bits on the output are correct.
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2022-04-08 12:29:15 -05:00 |
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