Byron Lathi
|
3c0bf9740c
|
Delete init hex on clean
|
2024-03-10 21:56:48 -07:00 |
|
Byron Lathi
|
d3914b3a51
|
Add sd io pins
|
2024-03-10 16:09:12 -07:00 |
|
Byron Lathi
|
cb426670cd
|
Do synthesis with sd controller
|
2024-03-10 12:29:08 -07:00 |
|
Byron Lathi
|
da41e60ee7
|
integrate sd controller and super simple tb
|
2024-03-10 11:31:07 -07:00 |
|
Byron Lathi
|
81382925f8
|
Update rtl common and sd controller submodules
|
2024-03-10 10:24:50 -07:00 |
|
Byron Lathi
|
96e014567d
|
Add sd controller submodule
|
2024-03-04 00:06:29 -08:00 |
|
Byron Lathi
|
358dfdbe75
|
Add sdram io to fpga
|
2024-03-03 23:31:02 -08:00 |
|
Byron Lathi
|
aee04b777a
|
Fix sdram sim
Just need to add the RTL_SIM define
|
2024-03-03 21:33:28 -08:00 |
|
Byron Lathi
|
10a72d8e1f
|
Add sdram, don't think it works though
|
2024-03-03 20:43:37 -08:00 |
|
Byron Lathi
|
01b1ecbcac
|
Add basic sim
|
2024-03-03 17:09:17 -08:00 |
|
Byron Lathi
|
ab9da189d1
|
Build software correctly, ignore debugger files
|
2024-03-03 14:50:40 -08:00 |
|
Byron Lathi
|
42fbc17a2a
|
Add test code and top level Makefile
|
2024-03-03 12:52:44 -08:00 |
|
Byron Lathi
|
cd1dfa39cb
|
Fix PLL settings, add cpu output clock
|
2024-03-03 09:45:04 -08:00 |
|
Byron Lathi
|
0752220b0e
|
Add basic project with cpu, ram and rom
|
2024-03-02 22:46:48 -08:00 |
|