Commit Graph

639 Commits

Author SHA1 Message Date
Byron Lathi
3c5cabd2be Update test, use scapy 2024-09-02 20:34:09 -07:00
Byron Lathi
30c7ed9c6a Start work on tx ctrl 2024-09-02 20:33:50 -07:00
Byron Lathi
f4ab7b456d Update so I can switch computers 2024-09-02 18:15:19 -07:00
Byron Lathi
1deceddcf6 update reg addr width, add fifo for m2s dma to write to 2024-09-02 14:48:57 -07:00
Byron Lathi
66855b050b Move m2s dma into the tcp streams 2024-09-02 12:55:36 -07:00
Byron Lathi
247033ea2d Uncomment module load
oops
2024-09-01 22:26:39 -07:00
Byron Lathi
73455e2be4 Remove sub from verilog-ethernet 2024-09-01 22:25:22 -07:00
Byron Lathi
dc90c00172 Mega commit to kick things off 2024-09-01 22:23:21 -07:00
Byron Lathi
8425d6a96e Remove mux/demus from dma 2024-08-29 18:37:04 -07:00
Byron Lathi
e440aa7bdb Change from ddr buffers to regular fifos 2024-08-29 18:33:52 -07:00
Byron Lathi
1bb613888f Show errors in log file 2024-08-29 18:27:33 -07:00
Byron Lathi
6f8e976a08 Add basic m2s code 2024-08-20 19:01:37 -07:00
Byron Lathi
9030f4b71d Separate ip streams 2024-08-20 18:57:24 -07:00
Byron Lathi
b2e56f4dca Clean up spacing 2024-08-20 18:57:08 -07:00
Byron Lathi
14f92c39fb Add blank stubs.list 2024-08-20 18:56:01 -07:00
Byron Lathi
759a57f0af Add new stream dma git repo 2024-08-20 18:47:13 -07:00
Byron Lathi
8d5393ca6e Changes before work 2024-08-20 08:27:17 -07:00
Byron Lathi
7b5fb1a682 Pass synthesis 2024-08-19 23:17:23 -07:00
Byron Lathi
b11be44446 Changes for synthesis 2024-08-19 23:09:32 -07:00
Byron Lathi
f492c5b23d Done for the day 2024-08-19 22:59:12 -07:00
Byron Lathi
752fce5b2e Update diagrams again (5) 2024-08-19 22:13:37 -07:00
Byron Lathi
e267fa4c37 Update diagrams again (4) 2024-08-19 21:42:36 -07:00
Byron Lathi
d85dc3e490 Update diagrams again (3) 2024-08-19 21:21:39 -07:00
Byron Lathi
b8b9852974 Update regs 2024-08-19 21:11:12 -07:00
Byron Lathi
47f958f5c4 Update regs 2024-08-19 20:27:27 -07:00
Byron Lathi
c857ffd8e5 Update diagrams again (2) 2024-08-19 19:12:55 -07:00
Byron Lathi
7e64ff1d6b Update diagrams again 2024-08-19 19:00:54 -07:00
Byron Lathi
8c9a4f7b9e Update drawing again 2024-08-19 18:41:55 -07:00
Byron Lathi
bcb5259f92 Update network_processor docs, add arp to diagram 2024-08-19 17:40:50 -07:00
Byron Lathi
8e87345f22 Add verilog ethernet 2024-08-19 17:40:16 -07:00
Byron Lathi
b521bbe5cf Move tcp into its own wrapper 2024-08-18 20:08:50 -07:00
Byron Lathi
a190a2d1c5 Update tcp with new buffer type 2024-08-18 16:41:12 -07:00
Byron Lathi
063f219f01 Add ntw files to project 2024-08-18 10:13:15 -07:00
Byron Lathi
8208bd6fa5 Use sram instead of sdram in sim, fully switch to verilator 2024-08-18 10:04:54 -07:00
Byron Lathi
9b2a40df06 Add tcp regs and switch to verilator 2024-08-17 11:56:01 -07:00
Byron Lathi
52a76e3a85 Add start of regs 2024-08-16 08:24:14 -07:00
Byron Lathi
7ba9658560 Update network_processor docs 2024-08-16 07:54:10 -07:00
Byron Lathi
6320af16ec Update diagram to static ports 2024-08-15 22:51:41 -07:00
Byron Lathi
c4eba333e8 Add start of tcp docs 2024-08-05 20:32:07 -07:00
Byron Lathi
bb125b0892 Merge branch '91-use-external-sd-card-controller' into 'AXI-Rewrite'
Resolve "Use External SD card controller"

Closes #91

See merge request bslathi19/super6502!72
2024-08-01 05:18:14 +00:00
Byron Lathi
82f5238a15 Update sdspi with merged version 2024-07-31 22:08:02 -07:00
Byron Lathi
434fc1b28a Fix sdspi, add missing source file 2024-07-31 22:02:47 -07:00
Byron Lathi
f99df72fe2 Update sdspi with write dma 2024-07-31 21:56:50 -07:00
Byron Lathi
e0f511df2e Add new DMA files to project config 2024-07-26 23:02:40 -07:00
Byron Lathi
383cb6d59e Add wait for DMA (should poll bit instead) 2024-07-26 22:58:31 -07:00
Byron Lathi
aa2e686b53 Update sdspi 2024-07-25 22:56:30 -07:00
Byron Lathi
5cd03a37eb Start working on axi dma 2024-07-22 00:07:04 -07:00
Byron Lathi
90c5c0dc94 Update SD version and start working on DMA 2024-07-21 18:58:35 -07:00
Byron Lathi
abb1668f14 Synthesis file updates 2024-07-20 21:51:28 -07:00
Byron Lathi
3d05d07541 Move shadow to us, get some commands going 2024-07-20 21:40:26 -07:00