Currently an interrupt is triggered any time there is any activity on
the UART_RXD line, but later it will only trigger once there is data
ready to be read.
Upon receiving an interrupt, the corresponding bit in the interrupt
status register will be set and an IRQ will be raised for the CPU. The
cpu can then respond to the interrupt and clear the interrupt by writing
back to the interrupt status register.
This also increases the number of registers to 4, one more for the high
pair of displays, and a final one for a mask register which has not been
implemented yet.
