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Integrate uart controller into top level module

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Adds new chip select for the UART, and a new entry in the data_out mux
for the UART.
This commit is contained in:
Byron Lathi
2022-03-14 10:45:45 -05:00
parent da4d5f0fe7
commit cfcf94a875
2 changed files with 11 additions and 4 deletions
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4
hw/fpga/addr_decode.sv
View File

@@ -2,11 +2,13 @@ module addr_decode(
input logic [15:0] addr,
output logic ram_cs,
output logic rom_cs,
output logic hex_cs
output logic hex_cs,
output logic uart_cs
);
assign rom_cs = addr[15];
assign ram_cs = ~addr[15] && addr < 16'h7ff0;
assign hex_cs = addr >= 16'h7ff0 && addr < 16'h7ff4;
assign uart_cs = addr >= 16'h7ff4 && addr < 16'h7ff6;
endmodule

11
hw/fpga/super6502.sv
View File

@@ -40,10 +40,12 @@ assign cpu_data = cpu_rwb ? cpu_data_out : 'z;
logic [7:0] rom_data_out;
logic [7:0] ram_data_out;
logic [7:0] uart_data_out;
logic ram_cs;
logic rom_cs;
logic hex_cs;
logic uart_cs;
cpu_clk cpu_clk(
.inclk0(clk_50),
@@ -65,7 +67,8 @@ addr_decode decode(
.addr(cpu_addr),
.ram_cs(ram_cs),
.rom_cs(rom_cs),
.hex_cs(hex_cs)
.hex_cs(hex_cs),
.uart_cs(uart_cs)
);
@@ -74,6 +77,8 @@ always_comb begin
cpu_data_out = ram_data_out;
else if (rom_cs)
cpu_data_out = rom_data_out;
else if (uart_cs)
cpu_data_out = uart_data_out;
else
cpu_data_out = 'x;
end
@@ -112,11 +117,11 @@ uart uart(
.rst(rst),
.rw(cpu_rwb),
.data_in(cpu_data_in),
.cs(),
.cs(uart_cs),
.addr(cpu_addr[1:0]),
.RXD(UART_RXD),
.TXD(UART_TXD),
.data_out()
.data_out(uart_data_out)
);
endmodule