Byron Lathi cfcf94a875 Integrate uart controller into top level module ...

Adds new chip select for the UART, and a new entry in the data_out mux
for the UART.

2022-03-14 10:45:45 -05:00

hw

Integrate uart controller into top level module

2022-03-14 10:45:45 -05:00

sw

Add uart tests

2022-03-14 00:47:26 -05:00

.gitlab-ci.yml

Update .gitlab-ci.yml

2022-03-10 22:27:43 +00:00

Description

No description provided

5.5 MiB

Languages

SystemVerilog 47.7%

Verilog 41.8%

Python 4.8%

VHDL 2%

Assembly 2%

Other 1.6%