Byron Lathi 1128b986eb Fix state transitions with regard to clock ...

The SD card expects data to transition on falling edges and be stable on
rising edges.

Additionally, writes from the CPU were not handled with correct timing.

Now, there is an extra state when writing to the command register so
that the command is properly latched before the CRC is calculated.

2022-04-10 17:52:07 -05:00

hw

Fix state transitions with regard to clock

2022-04-10 17:52:07 -05:00

sw

do a little test to see if memory mapping works

2022-04-07 12:43:47 -05:00

.gitlab-ci.yml

add testbench for SD command tx

2022-04-08 12:29:15 -05:00

Description

No description provided

5.5 MiB

Languages

SystemVerilog 47.7%

Verilog 41.8%

Python 4.8%

VHDL 2%

Assembly 2%

Other 1.6%