Byron Lathi 19b13164e9 RWB and ADDR are inputs, not outputs!

2022-12-19 23:43:45 -05:00

hw

RWB and ADDR are inputs, not outputs!

2022-12-19 23:43:45 -05:00

sw

Throw everything up

2022-10-04 17:15:49 -05:00

.gitlab-ci.yml

Change CI to ignore fpga build, kicad to symlink

2022-10-04 17:25:42 -05:00

.gitmodules

Use our own toolchain instead of the one in the image

2022-04-20 12:41:20 -05:00

Description

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5.5 MiB

Languages

SystemVerilog 47.7%

Verilog 41.8%

Python 4.8%

VHDL 2%

Assembly 2%

Other 1.6%