Byron Lathi 2084054d3d Add script for creating verilog filesystem image

2023-10-06 06:48:47 -07:00

hw

Increase sim time to get into sd block reads

2023-10-04 22:50:55 -07:00

sw

Add script for creating verilog filesystem image

2023-10-06 06:48:47 -07:00

.gitignore

Start spi controller and tb

2023-07-21 22:10:39 -07:00

.gitlab-ci.yml

Refactor makefile, update verilog-sd-emulator

2023-09-29 23:48:28 -07:00

.gitmodules

Resolve "Use dependencies instead of makefile chaining"

2023-09-30 04:16:52 +00:00

init_env.sh

Resolve "Run simulation as part of ci"

2023-09-30 05:05:12 +00:00

Description

No description provided

5.5 MiB

Languages

SystemVerilog 47.7%

Verilog 41.8%

Python 4.8%

VHDL 2%

Assembly 2%

Other 1.6%