Byron Lathi
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2084054d3d
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Add script for creating verilog filesystem image
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2023-10-06 06:48:47 -07:00 |
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Byron Lathi
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2b98ad1522
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Increase sim time to get into sd block reads
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2023-10-04 22:50:55 -07:00 |
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Byron Lathi
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e6e3044f25
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update sd emulator
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2023-10-04 20:27:25 -07:00 |
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Byron Lathi
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6a684f62f8
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Remove another wait, update sd emulator
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2023-10-04 20:24:56 -07:00 |
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Byron Lathi
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019b9c8120
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Update sd, remove wait state
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2023-10-04 19:11:45 -07:00 |
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Byron Lathi
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c1f7b33dda
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Update sd card emu
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2023-10-03 23:08:56 -07:00 |
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Byron Lathi
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3a211faed7
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Don't have sd wait in simulation
need to figure out how to set that RTL_SIM flag only when we are
compiling code for the sim
also bro the sim is like 8000x slower than irl.
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2023-09-30 17:40:01 -07:00 |
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Byron Lathi
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cc32430f2a
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Refactor makefile, update verilog-sd-emulator
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2023-09-29 23:48:28 -07:00 |
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Byron Lathi
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29aa369b33
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Merge branch 'master' into 34-sd-card-spi-mode-testbench
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2023-09-29 22:18:06 -07:00 |
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Byron Lathi
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6d49e752bf
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Merge branch '36-run-simulation-as-part-of-ci' into 'master'
Resolve "Run simulation as part of ci"
Closes #36
See merge request bslathi19/super6502!31
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2023-09-30 05:05:12 +00:00 |
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Byron Lathi
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f8bdbfbb2b
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Resolve "Run simulation as part of ci"
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2023-09-30 05:05:12 +00:00 |
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Byron Lathi
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907e5e9227
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Merge branch '33-use-dependencies-instead-of-makefile-chaining-2' into 'master'
Resolve "Use dependencies instead of makefile chaining"
Closes #33
See merge request bslathi19/super6502!30
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2023-09-30 04:16:52 +00:00 |
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Byron Lathi
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d3d3fea916
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Resolve "Use dependencies instead of makefile chaining"
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2023-09-30 04:16:52 +00:00 |
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Byron Lathi
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913351efd4
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Add sd emulator as submodule
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2023-09-28 23:09:47 -07:00 |
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Byron Lathi
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74f69378e8
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Merge branch '32-add-build-check-to-ci' into 'master'
Resolve "Add build check to CI"
See merge request bslathi19/super6502!27
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2023-09-29 05:14:52 +00:00 |
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Byron Lathi
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62967aa88d
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Resolve "Add build check to CI"
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2023-09-29 05:14:52 +00:00 |
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Byron Lathi
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624d662669
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Merge branch '32-add-build-check-to-ci' into 'master'
Resolve "Add build check to CI"
Closes #32
See merge request bslathi19/super6502!25
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2023-09-29 04:37:07 +00:00 |
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Byron Lathi
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df89962932
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remove env call
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2023-09-28 21:34:42 -07:00 |
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Byron Lathi
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d5bb93f9c9
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Fix the bad commit
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2023-09-28 21:30:38 -07:00 |
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Byron Lathi
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8d4e2a11b0
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Merge branch '32-add-build-check-to-ci' of https://git.byronlathi.com/bslathi19/super6502 into 32-add-build-check-to-ci
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2023-09-28 21:29:40 -07:00 |
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Byron Lathi
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d113498459
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Try a bad commit
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2023-09-28 21:28:39 -07:00 |
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Byron Lathi
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801732b5c8
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Merge branch 'add_ci' into '32-add-build-check-to-ci'
Update .gitlab-ci.yml file
See merge request bslathi19/super6502!26
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2023-09-29 04:25:54 +00:00 |
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Byron Lathi
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59f88ead3f
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Update .gitlab-ci.yml file
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2023-09-29 04:25:54 +00:00 |
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Byron Lathi
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1b838169d3
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Merge branch '31-show-uart-messages-in-sim-log' into 'master'
Resolve "Show UART messages in sim log"
Closes #31
See merge request bslathi19/super6502!24
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2023-09-28 06:14:00 +00:00 |
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Byron Lathi
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85f53816f9
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Remove unneeded CR
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2023-09-27 23:03:22 -07:00 |
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Byron Lathi
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4925354f53
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Fix uart status multiple drivers
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2023-09-27 23:02:53 -07:00 |
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Byron Lathi
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4d0abbb508
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Add sim uart
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2023-09-27 22:15:27 -07:00 |
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Byron Lathi
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a76763bdc7
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Merge branch '23-create-a-better-simulation-environment' into 'master'
Resolve "Create a better simulation environment"
Closes #23
See merge request bslathi19/super6502!23
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2023-09-28 04:16:59 +00:00 |
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Byron Lathi
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9e19a1eb72
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Disable sdr debug, initialize uart status
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2023-09-27 21:14:09 -07:00 |
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Byron Lathi
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ec4c3bab86
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Update verilog-6502 bslathi19/verilog-6502@aaf4c084ef
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2023-09-26 23:15:22 -07:00 |
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Byron Lathi
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915188e8f1
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New test program that causes the error
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2023-09-26 18:23:01 -07:00 |
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Byron Lathi
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c2dd5d616b
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Gate rdy behind sdram_cs #28
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2023-09-25 23:45:23 -07:00 |
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Byron Lathi
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4ee21f23b6
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Up the sim time
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2023-09-25 19:13:06 -07:00 |
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Byron Lathi
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95e05292cc
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Fix clocks, define RTL_SIM
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2023-09-24 23:58:32 -07:00 |
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Byron Lathi
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be68b4c9f9
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Change sdrclk and sysclk to have aligned rising edges
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2023-09-24 14:53:38 -07:00 |
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Byron Lathi
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3fcfa4d3ac
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Add REPO_TOP env var
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2023-09-24 10:35:17 -07:00 |
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Byron Lathi
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9bd031e35e
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Add support for test programs
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2023-09-24 10:29:32 -07:00 |
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Byron Lathi
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13ea5ca71b
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Add memory
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2023-09-24 10:06:23 -07:00 |
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Byron Lathi
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d3aa195adf
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Add updated sim cpu with fix
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2023-09-23 10:49:44 -07:00 |
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Byron Lathi
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00173f4e89
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Add submodule back
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2023-09-23 09:59:39 -07:00 |
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Byron Lathi
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77dd4f1002
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remove sim submodule
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2023-09-23 09:59:09 -07:00 |
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Byron Lathi
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bc0ab7eb54
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Fix infinite loop
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2023-09-22 19:46:25 -07:00 |
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Byron Lathi
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5e03795c09
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Get something simulated
Infinite loop being caused somewhere
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2023-09-21 23:22:17 -07:00 |
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Byron Lathi
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1f503b2d80
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update sim environment
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2023-09-21 20:35:52 -07:00 |
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Byron Lathi
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e50203dd3e
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Add generic SDR
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2023-09-21 19:23:31 -07:00 |
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Byron Lathi
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d37e32ec64
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Add sim cpu
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2023-09-18 23:27:54 -07:00 |
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Byron Lathi
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b30e4c73fb
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Merge branch '22-organize-project-better' into 'master'
Resolve "Organize Project Better"
Closes #22
See merge request bslathi19/super6502!22
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2023-09-19 02:57:26 +00:00 |
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Byron Lathi
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c466c62969
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Resolve "Organize Project Better"
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2023-09-19 02:57:26 +00:00 |
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Byron Lathi
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a770d938de
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Copy bios device functions to kernel
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2023-09-04 14:31:55 -07:00 |
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Byron Lathi
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791bffb248
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Add copy data back
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2023-09-04 14:08:52 -07:00 |
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