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Don't have sd wait in simulation

Browse Source 
need to figure out how to set that RTL_SIM flag only when we are
compiling code for the sim

also bro the sim is like 8000x slower than irl.
This commit is contained in:
Byron Lathi
2023-09-30 17:40:01 -07:00
parent cc32430f2a
commit 3a211faed7
4 changed files with 215 additions and 213 deletions
Download Patch File Download Diff File Expand all files Collapse all files

422
hw/efinix_fpga/init_hex.mem
View File

@@ -1,9 +1,9 @@
@00000000
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B1 1A 38 E9 30 90 2C C9 0A B0 28 20 A8 F6 48 A5
0C A6 0D 06 0C 26 0D 06 0C 26 0D 65 0C 85 0C 8A
65 0D 85 0D 06 0C 26 0D 68 65 0C 85 0C 90 D1 E6
0D B0 CD A5 0C A6 0D 60 AC 51 92 EE 51 92 99 52
92 60 A9 52 A2 92 18 6D 51 92 90 01 E8 4C 22 FD
A5 1C A6 1D 4C 22 FD 20 AF F6 EE 4B 92 D0 F8 EE
4C 92 D0 F3 60 20 50 F7 AD 66 92 AE 67 92 20 22
FD AD 68 92 AE 69 92 20 22 FD 4C 02 92 84 0C 20
E0 FB 20 42 F7 A5 0C 4C 10 FC 84 0C 20 E0 FB 20
42 F7 A5 0C 4C 51 FC 48 A0 05 B9 18 00 99 3F 92
88 10 F7 68 85 18 86 19 20 63 FB 85 1A 86 1B 20
63 FB 85 1C 86 1D A9 00 A8 91 1C C8 91 1C C8 B1
1C 8D 03 92 C8 B1 1C 8D 04 92 A5 1A 85 0C A5 1B
85 0D A0 00 B1 1A F0 0B C9 25 F0 07 C8 D0 F5 E6
1B D0 F1 98 18 65 1A 85 1A 90 02 E6 1B 38 E5 0C
85 0E A5 1B E5 0D 85 0F 05 0E F0 25 20 49 FB A0
05 A5 1D 91 04 88 A5 1C 91 04 88 A5 0D 91 04 88
A5 0C 91 04 88 A5 0F 91 04 88 A5 0E 91 04 20 02
92 20 A4 F6 AA D0 0B A2 05 BD 3F 92 95 18 CA 10
F8 60 C9 25 D0 09 B1 1A C9 25 D0 09 20 A8 F6 20
B2 F6 4C CA F7 A9 00 A2 0B 9D 46 92 CA 10 FA B1
1A C9 2D D0 05 8E 46 92 F0 19 C9 2B D0 05 8E 47
92 F0 10 C9 20 D0 05 8E 48 92 F0 07 C9 23 D0 09
8E 49 92 20 A8 F6 4C 4F F8 A2 20 C9 30 D0 06 AA
20 A8 F6 B1 1A 8E 4A 92 C9 2A D0 09 20 A8 F6 20
EE F6 4C 98 F8 20 FA F6 8D 4B 92 8E 4C 92 8C 4D
92 8C 4E 92 B1 1A C9 2E D0 1B 20 A8 F6 B1 1A C9
2A D0 09 20 A8 F6 20 EE F6 4C BF F8 20 FA F6 8D
4D 92 8E 4E 92 B1 1A C9 7A F0 19 C9 68 F0 15 C9
74 F0 11 C9 6A F0 08 C9 4C F0 04 C9 6C D0 0B A9
FF 8D 4F 92 20 A8 F6 4C C5 F8 8C 51 92 A2 52 8E
66 92 A2 92 8E 67 92 20 A8 F6 C9 63 D0 0D 20 EE
F6 8D 52 92 A2 00 A9 01 4C F1 F9 C9 64 F0 04 C9
69 D0 2D A2 00 AD 48 92 F0 02 A2 20 AD 47 92 F0
02 A2 2B 8E 50 92 20 DC F6 A4 07 30 0B AC 50 92
F0 06 8C 52 92 EE 51 92 A0 0A 20 7D F7 4C E8 F9
C9 6E D0 15 20 EE F6 85 0C 86 0D A0 00 B1 1C 91
0C C8 B1 1C 91 0C 4C CA F7 C9 6F D0 27 20 DC F6
AC 49 92 F0 17 48 86 14 05 14 05 06 05 07 0D 4D
92 0D 4E 92 F0 06 A9 30 20 38 F7 68 A0 08 20 7D
F7 4C E8 F9 C9 70 D0 0D A2 00 8E 4F 92 E8 8E 49
92 A9 78 D0 27 C9 73 D0 0C 20 EE F6 8D 66 92 8E
67 92 4C E8 F9 C9 75 D0 0B 20 D1 F6 A0 0A 20 8A
F7 4C E8 F9 C9 78 F0 04 C9 58 D0 29 48 AD 49 92
F0 0A A9 30 20 38 F7 A9 58 20 38 F7 20 D1 F6 A0
10 20 8A F7 68 C9 78 D0 09 AD 66 92 AE 67 92 20
7A FD 4C E8 F9 4C CA F7 AD 66 92 AE 67 92 20 64
FD 8D 68 92 8E 69 92 AD 4D 92 0D 4E 92 F0 15 AE
4D 92 EC 68 92 AD 4E 92 A8 ED 69 92 B0 06 8E 68
92 8C 69 92 38 AD 4B 92 ED 68 92 AA AD 4C 92 ED
69 92 B0 03 A9 00 AA 49 FF 8D 4C 92 8A 49 FF 8D
4B 92 AD 46 92 D0 03 20 5A F7 20 65 F7 AD 46 92
F0 03 20 5A F7 4C CA F7 A0 00 18 71 04 91 04 48
C8 8A 71 04 91 04 AA 68 60 C8 48 18 98 65 04 85
04 90 02 E6 05 68 60 A0 FF E0 80 B0 02 A0 00 84
06 84 07 60 E0 00 D0 06 AA D0 03 A9 01 60 A2 00
8A 60 A0 00 F0 07 A9 52 A2 F0 4C 05 92 60 A9 00
85 0C A9 F0 85 0D A9 00 85 0E A9 92 85 0F A2 CD
A9 FF 85 14 A0 00 E8 F0 0D B1 0C 91 0E C8 D0 F6
E6 0D E6 0F D0 F0 E6 14 D0 EF 60 8C 6A 92 88 88
98 18 65 04 85 0C A6 05 90 01 E8 86 0D A0 01 B1
0C AA 88 B1 0C 20 22 FD A5 0C A6 0D 20 E9 FD AC
6A 92 4C 5A FA 85 0C 86 0D 20 75 F0 4C F3 FA 85
0C 86 0D A0 00 B1 0C F0 0E C8 84 14 20 68 F0 A4
14 D0 F2 E6 0D D0 EE 60 E0 00 D0 15 4A AA BD B0
FE 90 05 4A 4A 4A 4A 18 29 0F AA BD A5 FE A2 00
60 38 A9 00 AA 60 A4 04 D0 02 C6 05 C6 04 60 A5
04 38 E9 02 85 04 90 01 60 C6 05 60 A5 04 38 E9
04 85 04 90 01 60 C6 05 60 A5 04 38 E9 06 85 04
90 01 60 C6 05 60 A5 04 38 E9 07 85 04 90 01 60
C6 05 60 A0 01 B1 04 AA 88 B1 04 E6 04 F0 05 E6
04 F0 03 60 E6 04 E6 05 60 A0 03 4C 5A FA A0 05
4C 5A FA A0 08 4C 5A FA 85 0C 86 0D A2 00 B1 0C
60 A0 01 B1 04 AA 88 B1 04 60 A0 03 B1 04 85 07
88 B1 04 85 06 88 B1 04 AA 88 B1 04 60 A2 00 18
65 04 48 8A 65 05 AA 68 60 18 49 FF 69 01 48 8A
49 FF 69 00 AA A5 06 49 FF 69 00 85 06 A5 07 49
FF 69 00 85 07 68 60 A9 00 AA A0 00 84 06 84 07
48 20 3C FB A0 03 A5 07 91 04 88 A5 06 91 04 88
8A 91 04 68 88 91 04 60 85 14 20 63 FB 85 0E 86
0F 85 10 86 11 20 F5 FC 20 63 FB 85 06 86 07 60
20 F8 FB A6 07 A4 14 C0 0A D0 39 A5 06 05 0D 05
0C D0 11 E0 80 D0 0D A0 0B B9 99 FE 91 0E 88 10
F8 4C 88 FC 8A 10 1D A9 2D A0 00 91 0E E6 0E D0
02 E6 0F A5 0C A6 0D 20 B9 FB 85 0C 86 0D 4C 54
FC 20 F8 FB A9 00 48 A0 20 A9 00 06 0C 26 0D 26
06 26 07 2A C5 14 90 04 E5 14 E6 0C 88 D0 EC A8
B9 89 FE 48 A5 0C 05 0D 05 06 05 07 D0 D9 A0 00
68 91 0E F0 03 C8 D0 F8 A5 10 A6 11 60 D0 06 A2
00 8A 60 D0 FA A2 00 A9 01 60 F0 F9 30 F7 A2 00
8A 60 F0 02 10 EF A2 00 8A 60 F0 E9 90 E7 A2 00
8A 60 F0 DB A2 00 8A 2A 60 20 E2 FC A6 11 F0 13
B1 0C 91 0E C8 B1 0C 91 0E C8 D0 F4 E6 0D E6 0F
CA D0 ED A6 10 F0 08 B1 0C 91 0E C8 CA D0 F8 4C
63 FB 85 10 86 11 20 F5 FC C8 B1 04 AA 86 0F 88
B1 04 85 0E 60 A0 01 B1 04 85 0D 88 B1 04 85 0C
4C 6B FB A9 01 4C 20 FD A0 00 B1 04 A4 04 F0 07
C6 04 A0 00 91 04 60 C6 05 C6 04 91 04 60 A9 00
A2 00 48 A5 04 38 E9 02 85 04 B0 02 C6 05 A0 01
8A 91 04 68 88 91 04 60 A0 00 91 04 C8 48 8A 91
04 68 60 85 0E 86 0F 20 F5 FC B1 0C D1 0E D0 0C
AA F0 10 C8 D0 F4 E6 0D E6 0F D0 EE B0 03 A2 FF
60 A2 01 60 85 0E 86 0F A2 00 A0 00 B1 0E F0 08
C8 D0 F9 E6 0F E8 D0 F4 98 60 85 0C 86 0D 85 0E
86 0F A0 00 B1 0C F0 14 20 0C FB 29 02 F0 06 B1
0C 69 20 91 0C C8 D0 EC E6 0D D0 E8 A5 0E A6 0F
60 20 63 FB 85 0E 86 0F E8 8E 31 92 AA E8 8E 30
92 20 F5 FC 20 63 FB 85 10 86 11 A0 00 84 14 B1
10 18 65 0E 91 10 C8 B1 10 65 0F 91 10 CE 30 92
F0 11 A4 14 B1 0C C8 D0 02 E6 0D 84 14 20 68 F0
4C CD FD CE 31 92 D0 EA 60 85 0C 86 0D A9 00 8D
2A 92 8D 2B 92 A0 01 B1 04 AA 88 B1 04 20 22 FD
A0 02 A9 2A 91 04 C8 A9 92 91 04 A5 0C A6 0D 20
97 F7 AD 2A 92 AE 2B 92 60 A9 32 85 0C A9 92 85
0D A9 00 A8 A2 00 F0 0A 91 0C C8 D0 FB E6 0D CA
D0 F6 C0 39 F0 05 91 0C C8 D0 F7 60 62 61 64 20
74 6F 6B 65 6E 3A 20 25 78 0A 00 53 75 63 63 65
73 73 0A 00 45 72 72 6F 72 0A 00 53 74 61 72 74
0A 00 6F 70 5F 63 6F 6E 64 20 65 72 72 6F 72 0A
00 49 46 20 43 6F 6E 64 0A 00 47 6F 20 49 44 4C
45 0A 00 25 32 78 00 0A 00 30 31 32 33 34 35 36
37 38 39 41 42 43 44 45 46 2D 32 31 34 37 34 38
33 36 34 38 00 00 01 02 0C 09 0A 10 40 50 A0 D0
66 66 66 66 A6 88 88 66 66 66 66 66 66 66 66 66
09 00 00 00 00 00 00 00 33 33 33 33 33 00 00 00
50 55 55 25 22 22 22 22 22 22 22 22 22 02 00 00
40 44 44 14 11 11 11 11 11 11 11 11 11 01 00 70
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00

2
hw/efinix_fpga/simulation/src/verilog-sd-emulator

Submodule hw/efinix_fpga/simulation/src/verilog-sd-emulator updated: a37857045c...2fc0f0737c

2
sw/bios/Makefile
View File

@@ -1,5 +1,5 @@
CC=../cc65/bin/cl65
CFLAGS=-T -t none -I. --cpu "65C02"
CFLAGS=-T -t none -I. --cpu "65C02" -DRTL_SIM
LDFLAGS=-C link.ld -m $(NAME).map
NAME=bios

2
sw/bios/devices/sd_card.c
View File

@@ -25,7 +25,9 @@ uint8_t SD_init()
}
}
#ifndef RTL_SIM
for (i = 0; i < 1000; i++);
#endif
SD_sendIfCond(res);
if(res[0] != SD_IN_IDLE_STATE)