Byron Lathi 3a211faed7 Don't have sd wait in simulation ...

need to figure out how to set that RTL_SIM flag only when we are
compiling code for the sim

also bro the sim is like 8000x slower than irl.

2023-09-30 17:40:01 -07:00

hw

Don't have sd wait in simulation

2023-09-30 17:40:01 -07:00

sw

Don't have sd wait in simulation

2023-09-30 17:40:01 -07:00

.gitignore

Start spi controller and tb

2023-07-21 22:10:39 -07:00

.gitlab-ci.yml

Refactor makefile, update verilog-sd-emulator

2023-09-29 23:48:28 -07:00

.gitmodules

Resolve "Use dependencies instead of makefile chaining"

2023-09-30 04:16:52 +00:00

init_env.sh

Resolve "Run simulation as part of ci"

2023-09-30 05:05:12 +00:00

Description

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5.5 MiB

Languages

SystemVerilog 47.7%

Verilog 41.8%

Python 4.8%

VHDL 2%

Assembly 2%

Other 1.6%