3a211faed7
need to figure out how to set that RTL_SIM flag only when we are compiling code for the sim also bro the sim is like 8000x slower than irl.
55 lines
1.3 KiB
Makefile
55 lines
1.3 KiB
Makefile
CC=../cc65/bin/cl65
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CFLAGS=-T -t none -I. --cpu "65C02" -DRTL_SIM
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LDFLAGS=-C link.ld -m $(NAME).map
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NAME=bios
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BIN=$(NAME).bin
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HEX=$(NAME).hex
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FPGA_IMG=$(REPO_TOP)/hw/efinix_fpga/init_hex.mem
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EFX_RUN=/home/byron/Software/efinity/2023.1/scripts/efx_run.py
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EFX_PRJ=/home/byron/Projects/super6502/hw/efinix_fpga/super6502.xml
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LISTS=lists
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TESTS=tests
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SRCS=$(wildcard *.s) $(wildcard *.c)
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SRCS+=$(filter-out $(wildcard tests/*), $(wildcard **/*.s)) $(filter-out $(wildcard tests/*), $(wildcard **/*.c))
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OBJS+=$(patsubst %.s,%.o,$(filter %s,$(SRCS)))
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OBJS+=$(patsubst %.c,%.o,$(filter %c,$(SRCS)))
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all: $(HEX)
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$(HEX): $(BIN)
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objcopy --input-target=binary --output-target=verilog $(BIN) $(HEX)
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cp boot2.bin ../fsdir
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cmp $(HEX) $(FPGA_IMG); \
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RETVAL=$$?; \
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if [ $$RETVAL -eq 0 ]; then \
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echo "SAME"; \
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else \
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echo "NOT SAME"; \
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cp bios.hex ../../hw/efinix_fpga/init_hex.mem; \
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echo "Update ROM or rebuild FPGA image!"; \
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fi
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$(BIN): $(OBJS)
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$(CC) $(CFLAGS) $(LDFLAGS) $(OBJS) -o $@
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%.o: %.c $(LISTS)
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$(CC) $(CFLAGS) -l $(LISTS)/$<.list -c $< -o $@
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%.o: %.s $(LISTS)
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$(CC) $(CFLAGS) -l $(LISTS)/$<.list -c $< -o $@
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$(LISTS):
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mkdir -p $(addprefix $(LISTS)/,$(sort $(dir $(SRCS))))
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.PHONY: clean
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clean:
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rm -rf $(OBJS) $(BIN) $(HEX) $(LISTS) $(NAME).map
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