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2600a23e59636f5fbdf4776113caad4cdbbf70ea
super6502/hw/fpga
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Byron Lathi 2600a23e59 Add memory_mapper testbench 
This testbench simply creates the memory mapper, adds a mapping to the
first entry, and then makes sure the addresses are correct after
enabling and disabling the memory mapper.
2022-04-05 17:20:23 -05:00
..
hvl
Add memory_mapper testbench
2022-04-05 17:20:23 -05:00
simulation/modelsim
Add memory_mapper testbench
2022-04-05 17:20:23 -05:00
.gitignore
ignore .sopcinfo
2022-03-17 13:53:07 -05:00
addr_decode.sv
Add memory mapper.
2022-04-05 17:10:42 -05:00
bb_spi_controller.sv
Add bb_spi_controller
2022-03-08 15:26:01 -06:00
board_io.sv
Add board-io, replace sevenseg in sw
2022-03-18 01:27:55 +00:00
cpu_clk.ppf
Add hex drivers
2022-03-11 18:25:55 -06:00
cpu_clk.qip
Add hex drivers
2022-03-11 18:25:55 -06:00
cpu_clk.v
Add hex drivers
2022-03-11 18:25:55 -06:00
HexDriver.sv
Add hex drivers
2022-03-11 18:25:55 -06:00
memory_mapper.sv
Add memory mapper.
2022-04-05 17:10:42 -05:00
rom.qip
Add boot rom
2022-03-05 18:12:27 -06:00
rom.v
Get the FPGA part working
2022-03-11 22:55:26 -06:00
sdram_platform.qsys
Add SDRAM controller (controller)
2022-03-17 13:31:56 -05:00
sdram.sv
Add memory mapper.
2022-04-05 17:10:42 -05:00
SevenSeg.sv
Implement enable byte in hw
2022-03-12 21:45:30 -06:00
super6502.qpf
Create quartus project
2022-03-05 16:38:12 -06:00
super6502.qsf
Add memory mapper.
2022-04-05 17:10:42 -05:00
super6502.sdc
Move SDRAM and state machine into its own file
2022-03-17 17:49:20 -05:00
super6502.sv
Add memory mapper.
2022-04-05 17:10:42 -05:00
uart.sv
Add receive logic to UART
2022-03-14 16:41:59 -05:00