Byron Lathi 50b0860137 Update testbench with more realistic timings ...

Updates the testbench to simulate writes with more correct timings.
Writes take two clock cycles since the cpu runs at half speed.

2022-04-10 17:50:49 -05:00

hw

Update testbench with more realistic timings

2022-04-10 17:50:49 -05:00

sw

do a little test to see if memory mapping works

2022-04-07 12:43:47 -05:00

.gitlab-ci.yml

add testbench for SD command tx

2022-04-08 12:29:15 -05:00

Description

No description provided

5.5 MiB

Languages

SystemVerilog 47.7%

Verilog 41.8%

Python 4.8%

VHDL 2%

Assembly 2%

Other 1.6%